Bonding substrates using solder surface tension during solder reflow for three dimensional self-alignment of substrates

US9704822B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9704822-B2
Application numberUS-201514936849-A
CountryUS
Kind codeB2
Filing dateNov 10, 2015
Priority dateNov 10, 2015
Publication dateJul 11, 2017
Grant dateJul 11, 2017

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Methods are provided for bonding substrates together using alignment structures and solder reflow techniques which achieve self-alignment in three dimensions, as well as semiconductor structures that are formed using such methods. A first alignment structure is formed on a bonding surface of a first substrate, which includes an alignment trench formed in the bonding surface of the first substrate. A second alignment structure is formed on a bonding surface of a second substrate, which includes a bonding pad with solder formed on the bonding pad. The first and second substrates are placed together with the solder of the second alignment structure in contact with the first alignment structure. A solder reflow process causes the solder to melt and flow into the alignment trench while pulling on the bonding pad to cause the second substrate to move into alignment with the first substrate in each of X, Y, and Z directions.

First claim

Opening claim text (preview).

We claim: 1. A method, comprising: forming a first alignment structure on a first substrate, wherein the first alignment structure comprises an alignment trench formed in a bonding surface of the first substrate; forming a second alignment structure on a bonding surface of a second substrate, wherein the second alignment structure comprises a bonding pad with solder formed on the bonding pad; placing the bonding surfaces of the first and second substrates together with at least a portion of the solder of the second alignment structure in contact with at least a portion of the first alignment structure; and performing a solder reflow process to cause the solder on the bonding pad to melt and flow into the alignment trench while pulling on the bonding pad to cause the second substrate to move into alignment with the first substrate in each of X, Y, and Z directions; wherein the second alignment structure further comprises one or more standoff pads formed on the bonding surface of the second substrate, wherein alignment in the Z direction comprises contacting the one or more standoff pads to the bonding surface of the first substrate; and wherein the one or more standoff pads and the bonding pad on the bonding surface of the second substrate have substantially equal thicknesses. 2. The method of claim 1 , wherein the first alignment structure further comprises a wetting layer that is formed to line the alignment trench and facilitate the flow of solder into the alignment trench. 3. The method of claim 1 , wherein alignment in the X and Y directions comprises laterally aligning a pattern of the alignment trench of the first substrate to a corresponding pattern of the bonding pad on the second substrate in both X and Y directions. 4. The method of claim 3 , wherein the alignment trench and bonding pad are formed with corresponding cross-shaped patterns. 5. The method of claim 1 , wherein the solder reflow process comprises a low temperature solder reflow process in which the solder has a melting point in a range of about 60 degrees Celsius to about 120 degrees Celsius to minimize thermal stress and warpage. 6. The method of claim 1 , wherein a volume of the solder formed on the bonding pad is less than an open cavity volume of the alignment trench. 7. The method of claim 1 , wherein the first substrate comprises a wafer or a glass substrate, and wherein the second substrate comprises a wafer. 8. The method of claim 1 , wherein the first substrate comprises a handler wafer or a glass handler, and the second substrate comprises a device wafer. 9. The method of claim 1 , wherein the first substrate comprises a wafer or package carrier, and wherein the second substrate comprises a semiconductor die. 10. A semiconductor structure formed by a process comprising: forming a first alignment structure on a first substrate, wherein the first alignment structure comprises an alignment trench formed in a bonding surface of the first substrate; forming a second alignment structure on a bonding surface of a second substrate, wherein the second alignment structure comprises a bonding pad with solder formed on the bonding pad; placing the bonding surfaces of the first and second substrates together with at least a portion of the solder of the second alignment structure in contact with at least a portion of the first alignment structure; and performing a solder reflow process to cause the solder on the bonding pad to melt and flow into the alignment trench while pulling on the bonding pad to cause the second substrate to move into alignment with the first substrate in each of X, Y, and Z directions; wherein the second alignment structure further comprises one or more standoff pads formed on the bonding surface of the second substrate, wherein alignment in the Z direction comprises contacting the one or more standoff pads to the bonding surface of the first substrate; and wherein the one or more standoff pads and the bonding pad on the bonding surface of the second substrate have substantially equal thicknesses. 11. The semiconductor structure of claim 10 , wherein the first alignment structure further comprises a wetting layer that is formed to line the alignment trench and facilitate the flow of solder into the alignment trench. 12. The semiconductor structure of claim 10 , wherein alignment in the X and Y directions comprises laterally aligning a pattern of the alignment trench of the first substrate to a corresponding Hall pattern of the bonding pad on the second substrate in both X and Y directions. 13. The semiconductor structure of claim 12 , wherein the alignment trench and bonding pad are formed with corresponding cross-shaped patterns. 14. The semiconductor structure of claim 10 , wherein a volume of the solder formed on the bonding pad is less than an open cavity volume of the alignment trench. 15. A method, comprising: forming a pattern of first alignment structures on each of a plurality of die sites on a bonding surface of a substrate, wherein each of the first alignment structures comprises an alignment trench formed in the bonding surface of the substrate; forming a pattern of second alignment structures on a bonding surface of each of a plurality of dies, wherein each of the second alignment structures comprises a bonding pad with solder formed on the bonding pad; placing each of the plurality of dies at a respective one of the plurality of dies sites on the bonding surface of the substrate, with at least a portion of the solder of the second alignment structures in contact with at least a portion of the corresponding first alignment structures; and performing a solder reflow process to cause the solder on the bonding pads to melt and flow into the corresponding alignment trenches while pulling on the bonding pads to cause each of the plurality of dies to move into alignment with the respective one of the plurality of dies sites in each of X, Y, and Z directions; wherein the second alignment structures further comprise one or more standoff pads formed on the bonding surfaces of the dies, wherein alignment in the Z direction comprises contacting the one or more standoff pads to the bonding surface of the substrate; and wherein for a given die, the one or more standoff pads and the bonding pad on the bonding surface of the given die have substantially equal thicknesses. 16. The method of claim 15 , wherein the plurality of dies comprise at least one of homogenous dies and heterogeneous dies with different sizes and different functions. 17. The method of claim 15 , wherein the first alignment structures further comprise a wetting layer that is formed to line the alignment trench and facilitate the flow of solder into the alignment trench. 18. The method of claim 15 , wherein alignment in the X and Y directions comprises laterally aligning patterns of the alignment trenches of the first substrate to corresponding patterns of the bonding pads of the dies in both X and Y directions. 19. The method of claim 18 , wherein the alignment trenches and bonding pads are formed with corresponding cross-shaped patterns. 20. The method of claim 15 , wherein the solder reflow process comprises a low temperature solder reflow process in which the solder has a melting point in a range of about 60 degrees Celsius to about 120 degrees Celsius to minimize thermal stress and warpage.

Assignees

Inventors

Classifications

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9704822B2 cover?
Methods are provided for bonding substrates together using alignment structures and solder reflow techniques which achieve self-alignment in three dimensions, as well as semiconductor structures that are formed using such methods. A first alignment structure is formed on a bonding surface of a first substrate, which includes an alignment trench formed in the bonding surface of the first substra…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H10W72/072. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 11 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).