Three dimensional self-alignment of flip chip assembly using solder surface tension during solder reflow

Patent metadata

Field	Value
Publication number	US-9606308-B2
Application number	US-201514634189-A
Country	US
Kind code	B2
Filing date	Feb 27, 2015
Priority date	Feb 27, 2015
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

Techniques are provided for flip-chip assembly and packaging of microelectronic, photonics and optoelectronic devices in which three-dimensional alignment of package components is achieved using solder surface tension during a solder reflow process to move one or more package components and align such components in X, Y and Z directions using mechanical stops and chip butting techniques.

First claim

We claim:

1. A method for assembling a semiconductor device, comprising:
providing a first chip comprising a cavity region defined by a recessed surface and a sidewall surface, wherein the first chip comprises an array of first bonding pads formed on the recessed surface of the first chip, wherein solder is disposed on the first bonding pads, wherein the first chip comprises a plurality of vertical standoff structures disposed on the recessed surface of the first chip, and wherein the first chip comprises first circuit components disposed on the sidewall surface;
providing a second chip, wherein the second chip comprises an array of second bonding pads and an alignment stop formed on a surface of the second chip, wherein the array of second bonding pads corresponds to the array of first bonding pads, and wherein the second chip comprises second circuit components disposed on a side surface of the second chip;
placing the second chip into an initial position in the cavity of the first chip with the array of second bonding pads facing the array of first bonding pads and with the second chip resting on top of the plurality of vertical standoff structures, wherein in the initial position, the first and second array of bonding pads are misaligned in a lateral X direction, and misaligned in a lateral Y direction, and wherein in the initial position, the first and second components are aligned in a vertical Z direction;
performing a solder reflow process to cause the solder on the first bonding pads to contact corresponding ones of the second bonding pads of the second chip and cause the second chip to move in both the lateral X and Y directions while sliding along the top surfaces of the vertical standoff structures, to thereby align the second circuit components of the second chip with the first circuit components of the first chip in the X, Y and Z directions,
wherein alignment is obtained in the X direction by contact between the alignment stop and at least one of the vertical standoff structures, and wherein alignment is obtained in the Y direction by contact between the sidewall surface of the first chip and the side surface of the second chip.

2. The method of claim 1 , wherein the first chip comprises a photonics chip and the second chip comprises a semiconductor laser chip.

3. The method of claim 1 , wherein the first circuit components comprise a plurality of semiconductor waveguide structures having inputs exposed on the sidewall surface of the first chip, and wherein the second circuit components comprise semiconductor waveguides having outputs exposed on the side surface of the second chip.

4. The method of claim 1 , wherein in the initial position, a gap exists between the solder and second bonding pads of the second chip, wherein a size G of the gap is in a range of 0.15×H 1 <G<0.25×H 1 , wherein H 1 is a height of the vertical standoff structures.

5. The method of claim 1 , wherein the solder reflow process is performed using a vapor phase flux.

6. The method of claim 1 , wherein upon alignment of the first and second circuit components in the X, Y and Z directions, there remains misalignment between corresponding ones of the first and second bonding pads in at least one of the X direction and Y direction.

7. The method of claim 1 , wherein the at least one vertical standoff structure which contacts the alignment stop has a larger cross-sectional area than other vertical standoff structures that do not contact the alignment stop.

8. The method of claim 1 , wherein the first circuit components are disposed in protruding portions formed on the sidewall surface of the first chip.

9. The method of claim 1 , wherein in the initial position, the first and second array of bonding pads are misaligned in the lateral X and Y directions in an amount greater than about 10 μm.

10. The method of claim 1 , wherein during the solder reflow process, alignment between the first and second circuit components in the Z direction is maintained by keeping the surface of the second chip in contact with the top surface of the vertical standoff structures.

11. A semiconductor device that is fabricated using a method comprising:
providing a first chip comprising a cavity region defined by a recessed surface and a sidewall surface, wherein the first chip comprises an array of first bonding pads formed on the recessed surface of the first chip, wherein solder is disposed on the first bonding pads, wherein the first chip comprises a plurality of vertical standoff structures disposed on the recessed surface of the first chip, and wherein the first chip comprises first circuit components disposed on the sidewall surface;
providing a second chip, wherein the second chip comprises an array of second bonding pads and an alignment stop formed on a surface of the second chip, wherein the array of second bonding pads corresponds to the array of first bonding pads, and wherein the second chip comprises second circuit components disposed on a side surface of the second chip;
placing the second chip into an initial position in the cavity of the first chip with the array of second bonding pads facing the array of first bonding pads and with the second chip resting on top of the plurality of vertical standoff structures, wherein in the initial position, the first and second array of bonding pads are misaligned in a lateral X direction, and misaligned in a lateral Y direction, and wherein in the initial position, the first and second components are aligned in a vertical Z direction;
performing a solder reflow process to cause the solder on the first bonding pads to contact corresponding ones of the second bonding pads of the second chip and cause the second chip to move in both the lateral X and Y directions while sliding along the top surfaces of the vertical standoff structures, to thereby align the second circuit components of the second chip with the first circuit components of the first chip in the X, Y and Z directions,
wherein alignment is obtained in the X direction by contact between the alignment stop and at least one of the vertical standoff structures, and wherein alignment is obtained in the Y direction by contact between the sidewall surface of the first chip and the side surface of the second chip.

12. The semiconductor device of claim 11 , wherein the first chip comprises a photonics chip and the second chip comprises a semiconductor laser chip.

13. The semiconductor device of claim 11 , wherein the first circuit components comprise a plurality of semiconductor waveguide structures having inputs exposed on the sidewall surface of the first chip, and wherein the second circuit components comprise semiconductor waveguides having outputs exposed on the side surface of the second chip.

14. The semiconductor device of claim 11 , wherein in the initial position, a gap exists between the solder and second bonding pads of the second chip, wherein a size G of the gap is in a range of 0.15×H 1 <G<0.25×H 1 , wherein H 1 is a height of the vertical standoff structures.

15. The semiconductor device of claim 11 , wherein the solder reflow process is performed using a vapor phase flux.

16. The semiconductor device of claim 11 , wherein upon alignment of the first and second circuit components in the X, Y and Z directions, there remains misalignment between corresponding ones of the first and second bonding pads in at least one of the X direction and Y direction.

17. The semiconductor device of claim 11 , wherein the at least one vertical standoff structure which contacts the alignment stop has a larger cross-section

Assignees

• IBM

Inventors

• Barwicz Tymon
• Martin Yves C
• Nah Jae-Woong

Classifications

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title