Supercomputer using wafer scale integration

Patent metadata

Field	Value
Publication number	US-9568960-B2
Application number	US-201514627657-A
Country	US
Kind code	B2
Filing date	Feb 20, 2015
Priority date	Feb 20, 2015
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

A semiconductor structure includes a substrate with cooling layers, cooling channels, coolant inlets and outlets in fluid communication with the cooling channels, and a device layer on the cooling layers with one or more connection points and a device layer area. The device layer thermal coefficient of expansion is substantially equal to that of the cooling layers. A plurality of laminate substrates are disposed on, and electrically attached to, the device layer. The laminate substrate thermal coefficient of expansion differs from that of the device layer, each laminate substrate is smaller than the device layer portion to which it is attached, and each laminate substrate includes gaps between sides of adjacent laminate substrates. The laminate substrates are not electrically or mechanically connected to each other across the gaps therebetween and the laminate substrates are small enough to prevent warping of the device, interconnection and cooling layers due to thermal expansion.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a substrate that includes one or more cooling layers, one or more cooling channels, one or more coolant inlets and outlets in fluid communication with the cooling channels, a device layer disposed on the cooling layers that has one or more connection points and a device layer area, wherein a device layer thermal coefficient of expansion is substantially equal to that of the one or more cooling layers;
a plurality of laminate substrates arranged in an array that are disposed on, and electrically attached to, the device layer, wherein a laminate substrate thermal coefficient of expansion differs from that of the device layer, and each laminate substrate is smaller in area than an area of the device layer portion to which it is attached, and each laminate substrate includes sides with, gaps between sides of adjacent laminate substrates,
wherein the laminate substrates are not electrically or mechanically connected to each other across the gaps between laminate substrates and the laminate substrates are small enough to substantially prevent warping and unacceptable stress of the device layer, interconnection and cooling layers due to thermal expansion.

2. The semiconductor structure of claim 1 , wherein the laminate substrates comprise one or more of a PC board, a ceramic or glass substrate, and a built-up organic substrate and the device layer is rigidly attached to the cooling layers by a material with a high thermal conductivity.

3. The semiconductor structure of claim 1 , wherein the device layer comprises one or more semiconductor wafers.

4. The semiconductor structure of claim 1 , wherein the substrate comprise one or more of glass and a semiconductor material.

5. The semiconductor structure of claim 1 , wherein the connection points comprise C4 micro solder balls disposed between the device layer and the laminate substrates.

6. The semiconductor structure of claim 1 , further comprising
a plurality of semiconductor structures,
a wafer gap between each semiconductor structure, and
one or more electrical connections between laminate substrates on different semiconductor structures across the wafer gaps,
wherein one or more of the coolant inlets and outlets of each semiconductor structure are connected to form a common cooling system.

7. A data processing structure comprising:
a semiconductor processor wafer containing two or more chips interconnected by on chip wiring levels rigidly attached on a non-device side of the semiconductor processor wafer to a liquid cooled substrate with a thermal coefficient of expansion substantially similar to that of the semiconductor processor wafer,
wherein substrates of each chip are attached to individual chips on a device side of each wafer.

8. The data processing structure of claim 7 , wherein the chip substrates are smaller in area than the chips on the wafer.

9. The data processing structure of claim 7 , further comprising one or more cards attached to each chip substrate, wherein a major surface of each card is perpendicular to a surface of the semiconductor processor wafer.

10. The data processing structure of claim 7 , further comprising one or more additional wafers stacked between the semiconductor processor wafer and the chip substrates that are electrically interconnected with the semiconductor processor wafer and the chip substrates.

11. A super computer structure, comprising;
two or more semiconductor processor wafers, each containing two or more chips interconnected by on chip wiring levels rigidly attached on a non-device side of the semiconductor processor wafer to one or more silicon microchannel wafers which are attached to a common set of manifold layers to provide liquid cooling; and
interconnect substrates configured to provide signaling between adjacent semiconductor processor wafers,
wherein the manifold layers have a thermal coefficient of expansion substantially similar to that of the silicon microchannel wafers, and
chip substrates are attached to each chip on a device side of the semiconductor processor wafer.

12. The data processing structure of claim 11 , wherein the manifold layers comprise one or more of integrated glass or silicon layers, and one or more stacked silicon layers.

13. The data processing structure of claim 11 , wherein the semiconductor processor wafers include multiple stacked wafers that are integrated by vertical interconnections.

14. The data processing structure of claim 11 , wherein the semiconductor processor wafers include one or more of a memory wafer, a processor wafers, and a field programmable gate array (FPGA).

15. The data processing structure of claim 11 , wherein each chip substrate comprises one of an organic material, a ceramic material, or a silicon material, and each chip substrate is configured to provide the semiconductor processor wafer with power, voltage regulation, and signal communication.

16. The data processing structure of claim 11 , wherein signaling between adjacent semiconductor processor wafers uses one or more electrical signals and optical signals.

Assignees

• IBM

Inventors

• Colgan Evan G
• Denneau Monty M
• Knickerbocker John

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/07236

  Soldering or alloying · CPC title