Vacuum channel transistor structures with sub-10 nanometer nanogaps and layered metal electrodes

Patent metadata

Field	Value
Publication number	US-11651925-B2
Application number	US-202117146515-A
Country	US
Kind code	B2
Filing date	Jan 12, 2021
Priority date	Sep 26, 2018
Publication date	May 16, 2023
Grant date	May 16, 2023

Abstract

A technique relates to a semiconductor device. An emitter electrode and a collector electrode are formed in a dielectric layer such that a nanogap separates the emitter electrode and the collector electrode, a portion of the emitter electrode including layers. A channel is formed in the dielectric layer so as to traverse the nanogap. A top layer is formed over the channel so as to cover the channel and the nanogap without filling in the channel and the nanogap, thereby forming a vacuum channel transistor structure.

First claim

What is claimed is:

1. A semiconductor device comprising:
an emitter electrode and a collector electrode formed in a dielectric layer such that a nanogap separates the emitter electrode and the collector electrode, a portion of the emitter electrode comprising layers;
a channel formed in the dielectric layer so as to traverse the nanogap; and
a top layer over the channel so as to cover the channel and the nanogap without filling in the channel and the nanogap, thereby forming a vacuum channel transistor structure, wherein vent holes are above the channel and adjacent to the nanogap.

2. The semiconductor device of claim 1 , wherein a dielectric material is formed on a global backgate underlying the channel.

3. The semiconductor device of claim 1 , wherein the emitter electrode and the collector electrode are formed on a high-k dielectric material.

4. The semiconductor device of claim 3 , wherein the high-k dielectric material is formed on a local bottom gate.

5. The semiconductor device of claim 1 , wherein the emitter electrode comprises an emitter tip opposing a collector tip of the collector electrode such that the nanogap is formed between the emitter and collector tips.

6. The semiconductor device of claim 5 , wherein the emitter tip comprises the layers.

7. The semiconductor device of claim 5 , wherein the collector tip comprises the layers.

8. The semiconductor device of claim 5 , wherein the layers comprise at least one low workfunction material interposed in a high workfunction material.

9. The semiconductor device of claim 1 , wherein the layers comprise one or more low workfunction layers and one or more high workfunction layers.

10. The semiconductor device of claim 1 , wherein the emitter electrode comprises a plurality of electrode tips opposing one or more collector tips of the collector electrode in the channel.

11. The semiconductor device of claim 1 , wherein the channel is a vacuum environment.

12. A semiconductor device comprising:
an emitter electrode and a collector electrode formed in a dielectric layer such that a nanogap separates the emitter electrode and the collector electrode, a portion of the emitter electrode comprising layers;
a channel formed in the dielectric layer so as to traverse the nanogap; and
a top layer over the channel so as to cover the channel and the nanogap without filling in the channel and the nanogap, thereby forming a vacuum channel transistor structure, wherein vent holes are formed in the top layer.

13. The semiconductor device claim 1 , wherein a cover material is formed over the vent holes in the top layer such that the cover material seals the channel in a vacuum environment.

14. A semiconductor device comprising:
an emitter electrode and a collector electrode formed in a dielectric layer such that a nanogap separates the emitter electrode and the collector electrode, a portion of the emitter electrode comprising layers of low workfunction material and high workfunction material, the emitter electrode comprising one or more elongated emitter tips, the collector electrode comprising one or more elongated collector tips;
a channel formed in the dielectric layer so as to traverse the nanogap;
a top layer over the channel so as to cover the channel and the nanogap without filling in the channel and the nanogap;
one or more vent holes formed in the top layer so as to communicate with the channel; and
a cover material sealing the one or more vent holes.

15. The semiconductor device of claim 14 , wherein a dielectric material is formed on a global backgate underlying the channel.

16. The semiconductor device of claim 14 , wherein the emitter electrode and the collector electrode are formed on a high-k dielectric material.

17. The semiconductor device of claim 16 , wherein the high-k dielectric material is formed on a local bottom gate.

18. The semiconductor device of claim 14 , wherein the emitter electrode comprises an emitter tip opposing a collector tip of the collector electrode such that the nanogap is formed between the emitter and collector tips.

19. The semiconductor device of claim 18 , wherein the emitter tip comprises the layers.

20. The semiconductor device of claim 18 , wherein the collector tip comprises the layers.

Assignees

• IBM

Inventors

• Smith Joshua T
• Wunsch Benjamin

Classifications

• H10P32/30

  Diffusion for doping of conductive or resistive layers · CPC title

• H10P76/202

  for lift-off processes · CPC title

• H10D64/251

  Source or drain electrodes for field-effect devices · CPC title

• H01J1/3042 Primary

  microengineered, e.g. Spindt-type · CPC title

• H01J21/105 Primary

  with microengineered cathode and control electrodes, e.g. Spindt-type · CPC title