Semiconductor device and related manufacturing method

Patent metadata

Field	Value
Publication number	US-9715987-B2
Application number	US-201414558050-A
Country	US
Kind code	B2
Filing date	Dec 2, 2014
Priority date	Apr 1, 2014
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

A semiconductor device may include the following elements: a semiconductor substrate, an insulator positioned on the substrate, a source electrode positioned on the insulator, a drain electrode positioned on the insulator, a gate electrode positioned between the source electrode and the drain electrode, a hollow channel surrounded by the gate electrode and positioned between the source electrode and the drain electrode, a dielectric member positioned between the hollow channel and the gate electrode, a first insulating member positioned between the gate electrode and the source electrode, and a second insulating member positioned between the gate electrode and the drain electrode.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, the method comprising:
preparing a substrate structure that includes a semiconductor substrate and an insulating layer;
forming a sacrificial layer on the insulating layer;
using the sacrificial layer to form a wire;
forming a dielectric member that surrounds the wire;
forming a gate electrode that surrounds the dielectric member;
removing the wire for forming a hollow channel that is surrounded by the gate electrode;
forming a first insulating member and a second insulating member;
forming a source electrode such that the first insulating member is positioned between the gate electrode and the source electrode; and
forming a drain electrode such that the second insulating member is positioned between the gate electrode and the drain electrode.

2. The method of claim 1 , further comprising:
removing two portions of a dielectric layer that are located at two ends of the gate electrode for forming the dielectric member; and
removing two portions of the sacrificial layer that are located at the two ends of the gate electrode for forming the wire.

3. The method of claim 1 , further comprising:
forming a first sidewall at the first insulating member before the forming the source electrode, wherein a portion of the first sidewall is positioned between the first insulating member and the source electrode after the forming the source electrode; and
forming a second sidewall at the second insulating member before the forming the drain electrode, wherein a portion of the second sidewall is positioned between the second insulating member and the drain electrode after the forming the drain electrode.

4. The method of claim 3 , wherein at least one of the first sidewall and the second sidewall is formed of a low work function material.

5. The method of claim 4 , wherein the annealing is performed at a temperature that is in a range of 600° C. to 1300° C.

6. The method of claim 3 , further comprising: performing annealing using an atmosphere that includes at least one of H 2 and N 2 such that at least one of the first sidewall and the second sidewall includes a curved surface that is convex toward the hollow channel.

7. The method of claim 1 , further comprising: at least one of providing an inert gas in the hollow channel and evacuating the hollow channel.

8. The method of claim 1 , wherein the hollow channel has at least one of a circular cylindrical structure, an oval cylindrical structure, a circular frustum structure, an oval frustum structure, a circular cone structure.

9. The method of claim 1 , further comprising:
patterning the sacrificial layer and the insulating layer to form a fin structure that includes a portion of the sacrificial layer and a portion of the insulating layer;
removing the portion of the insulating layer; and
performing annealing on the portion of the sacrificial layer to form the wire.

10. The method of claim 9 , wherein the annealing is performed using an atmosphere that includes at least one of He, N 2 , Ar, and H 2 .

11. The method of claim 9 , wherein the removing the portion of the insulating layer includes etching the portion of the insulating layer using at least one of a buffered oxide etch solution and a diluted hydrofluoric acid solution.

12. The method of claim 1 , wherein the sacrificial layer is formed of at least one of Al, polycrystalline silicon, Cr, Mo, W, Fe, Co, Cu, Ga, In, and Ti.

Assignees

• Semiconductor Mfg Int Shanghai Corp

Inventors

• Xiao Deyuan

Classifications

• H01J21/06 Primary

  having electrostatic control means only · CPC title

• H01J9/385

  Exhausting vessels · CPC title

• H01J9/24

  Manufacture or joining of vessels, leading-in conductors or bases · CPC title

• H01J19/38

  Control electrodes, e.g. grid · CPC title

• H01J9/148

  of electron emission flat panels, e.g. gate electrodes, focusing electrodes or anode electrodes · CPC title