Carbon nanotube vacuum transistors

Patent metadata

Field	Value
Publication number	US-9680116-B2
Application number	US-201514843332-A
Country	US
Kind code	B2
Filing date	Sep 2, 2015
Priority date	Sep 2, 2015
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

Vacuum transistors with carbon nanotube as the collector and/or emitter electrodes are provided. In one aspect, a method for forming a vacuum transistor includes the steps of: covering a substrate with an insulating layer; forming a back gate(s) in the insulating layer; depositing a gate dielectric over the back gate; forming a carbon nanotube layer on the gate dielectric; patterning the carbon nanotube layer to provide first/second portions thereof over first/second sides of the back gate, separated from one another by a gap G, which serve as emitter and collector electrodes; forming a vacuum channel in the gate dielectric; and forming metal contacts to the emitter and collector electrodes. Vacuum transistors are also provided.

First claim

What is claimed is:

1. A method for forming a vacuum transistor, the method comprising the steps of:
covering a substrate with an insulating layer;
forming at least one back gate in the insulating layer;
depositing a gate dielectric on the insulating layer over the back gate;
forming a carbon nanotube layer on the gate dielectric over the back gate;
patterning the carbon nanotube layer to provide a first portion of the carbon nanotube layer over a first side of the back gate and a second portion of the carbon nanotube layer over a second side of the back gate, wherein the first portion the carbon nanotube layer and the second portion of the carbon nanotube layer are separated from one another by a gap G, and wherein the first portion of the carbon nanotube layer serves as an emitter electrode of the vacuum transistor and the second portion of the carbon nanotube layer serves as a collector electrode of the vacuum transistor;
forming a vacuum channel in the gate dielectric over the back gate, wherein the vacuum channel is formed in the gate dielectric using an isotropic etching process; and
forming metal contacts to the emitter electrode and to the collector electrode.

2. The method of claim 1 , wherein the at least one back gate comprises a metal back gate.

3. The method of claim 1 , wherein a top surface of the at least one back gate is coplanar with a top surface of the insulating layer.

4. The method of claim 1 , wherein the at least one back gate is embedded in the insulating layer with a portion of the insulating layer separating the back gate from the substrate.

5. The method of claim 1 , wherein the carbon nanotube layer comprises either single-wall or multi-wall carbon nanotubes.

6. The method of claim 1 , wherein the carbon nanotube layer is patterned using oxygen plasma etching.

7. The method of claim 1 , wherein the gap G is from about 5 nm to about 100 nm, and ranges therebetween.

8. The method of claim 1 , wherein the vacuum channel is formed having a width W of from about 10 nm to about 150 nm, and ranges therebetween.

9. The method of claim 8 , wherein the width W is greater than the gap G.

10. A method for forming a vacuum transistor, the method comprising the steps of:
covering a substrate with an insulating layer;
forming at least one back gate in the insulating layer;
depositing a gate dielectric on the insulating layer over the back gate;
forming a carbon nanotube layer on the gate dielectric over the back gate;
patterning the carbon nanotube layer to provide a portion of the carbon nanotube layer over only a first side of the back gate, wherein the portion of the carbon nanotube layer serves as an emitter electrode of the vacuum transistor;
forming a vacuum channel in the gate dielectric over the back gate, wherein the vacuum channel is formed in the gate dielectric using an isotropic etching process;
forming a first metal contacts to the emitter electrode; and
forming a second metal contact on the gate dielectric over a second side of the back gate, wherein the second metal contact serves as a collector electrode of the vacuum transistor, and wherein the portion the carbon nanotube layer and the second metal contact are separated from one another by a gap G′.

11. The method of claim 10 , wherein a top surface of the at least one back gate is coplanar with a top surface of the insulating layer.

12. The method of claim 10 , wherein the at least one back gate is embedded in the insulating layer with a portion of the insulating layer separating the back gate from the substrate.

13. The method of claim 10 , wherein the carbon nanotube layer is patterned using oxygen plasma etching.

14. The method of claim 10 , wherein the gap G′ is from about 5 nm to about 100 nm, and ranges therebetween.

15. The method of claim 10 , wherein the vacuum channel is formed having a width W′ of from about 10 nm to about 150 nm, and ranges therebetween.

16. The method of claim 15 , wherein the width W′ is greater than the gap G′.

Assignees

• IBM

Inventors

• Cao Qing
• Cheng Kangguo
• Li Zhengwen
• Liu Fei

Classifications

• H10K10/43

  Bipolar transistors, e.g. organic bipolar junction transistors [OBJT] · CPC title

• H10K10/486

  the channel region comprising two or more active layers, e.g. forming pn heterojunctions · CPC title

• H01J21/105 Primary

  with microengineered cathode and control electrodes, e.g. Spindt-type · CPC title

• H01L51/0017

  Electricity · mapped topic

• H01L51/0558 Primary

  Electricity · mapped topic