Low voltage nanoscale vacuum electronic devices

US9331189B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9331189-B2
Application numberUS-201313888493-A
CountryUS
Kind codeB2
Filing dateMay 7, 2013
Priority dateMay 9, 2012
Publication dateMay 3, 2016
Grant dateMay 3, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An electronic device including a first conducting layer, a second conducting layer, and an insulating layer provided between the conducting layers. At least one side wall extends from the first conducting layer to the second conducting layer and includes at least a portion of the first conducting layer, the second conducting layer and the insulating layer. A bias voltage is applied between the first and second conducting layers, wherein responsive to the bias voltage, a two dimensional electron system is induced at least in one of the first conducting layer and the second conducting layer, and wherein electrons from the two dimensional electron system are emitted from the side wall side wall as a result of Coulombic repulsion and travel in air from the one of the first conducting layer and the second conducting layer to the other of the first conducting layer and the second conducting layer.

First claim

Opening claim text (preview).

What is claimed is: 1. An electronic device, comprising: a first conducting layer; a second conducting layer; and an insulating layer provided between the first conducting layer and the second conducting layer; wherein the electronic device includes at least one side wall that extends from the first conducting layer to the second conducting layer and that includes at least a portion of each of the first conducting layer, the second conducting layer and the insulating layer, wherein the electronic device is structured such that responsive to a bias voltage being applied between the first conducting layer and the second conducting layer, a two dimensional electron system is induced in at least one of the first conducting layer and the second conducting layer, and such that electrons from the two dimensional electron system are emitted from the at least one side wall side wall as a result of Coulombic repulsion and travel in air from the one of the first conducting layer and the second conducting layer to the other of the first conducting layer and the second conducting layer, wherein the first and second conducting layers are made of conductive materials that can provide mobile charge carriers (electrons or holes) and may include metal, semiconductor, oxide semiconductor, graphene and graphite material, and the insulating layer is made of an insulating material and may include air/vacuum and dielectric material such as oxide, nitride, wide bandgap semiconductor material, and wherein the conductive material is n-type silicon semiconductor, wherein responsive to the bias voltage the two dimensional electron system is induced in the second conducting layer, and wherein the electrons emitted from the at least one side wall travel in air from the second conducting layer to the first conducting layer. 2. The electronic device according to claim 1 , wherein the second conducting layer includes a semiconductor substrate comprising the semiconductor material coupled to a metal electrode. 3. The electronic device according to claim 2 , wherein the metal material is Al. 4. An electronic device, comprising: a first conducting layer; a second conducting layer; and an insulating layer provided between the first conducting layer and the second conducting layer; wherein the electronic device includes at least one side wall that extends from the first conducting layer to the second conducting layer and that includes at least a portion of each of the first conducting layer, the second conducting layer and the insulating layer, wherein the electronic device is structured such that responsive to a bias voltage being applied between the first conducting layer and the second conducting layer, a two dimensional electron system is induced in at least one of the first conducting layer and the second conducting layer, and such that electrons from the two dimensional electron system are emitted from the at least one side wall side wall as a result of Coulombic repulsion and travel in air from the one of the first conducting layer and the second conducting layer to the other of the first conducting layer and the second conducting layer, wherein the first and second conducting layers are made of conductive materials that can provide mobile charge carriers (electrons or holes) and may include metal, semiconductor, oxide semiconductor, graphene and graphite material, and the insulating layer is made of an insulating material and may include air/vacuum and dielectric material such as oxide, nitride, wide bandgap semiconductor material, and wherein the conductive material is p-type silicon semiconductor, wherein responsive to the bias voltage the two dimensional electron system is induced in the first conducting layer, and wherein the electrons emitted from the at least one side wall travel in air from the first conducting layer to the second conducting layer. 5. An electronic device, comprising: a first conducting layer; a second conducting layer; and an insulating layer provided between the first conducting layer and the second conducting layer; wherein the electronic device includes at least one side wall that extends from the first conducting layer to the second conducting layer and that includes at least a portion of each of the first conducting layer, the second conducting layer and the insulating layer, wherein the electronic device is structured such that responsive to a bias voltage being applied between the first conducting layer and the second conducting layer, a two dimensional electron system is induced in at least one of the first conducting layer and the second conducting layer, and such that electrons from the two dimensional electron system are emitted from the at least one side wall side wall as a result of Coulombic repulsion and travel in air from the one of the first conducting layer and the second conducting layer to the other of the first conducting layer and the second conducting layer, and wherein a thickness of the insulating layer is on the same order as or less than a mean free path of electrons in air (˜60 nm). 6. The electronic device according to claim 5 , wherein the first and second conducting layers are made of conductive materials that can provide mobile charge carriers (electrons or holes) and may include metal, semiconductor, oxide semiconductor, graphene and graphite material, and the insulating layer is made of an insulating material and may include air/vacuum and dielectric material such as oxide, nitride, wide bandgap semiconductor material. 7. The electronic device according to claim 6 , wherein the insulating material is SiO 2 . 8. The electronic device according to claim 5 , wherein the at least one side wall comprises a cleaved edge that extends from a top surface of the first conducting layer to a bottom surface of the second conducting layer. 9. The electronic device according to claim 5 , wherein the electronic device includes a void channel extending at least from the bottom surface of the first conducting layer through the insulating layer and to the top surface of the second conducting layer, wherein the at least one side wall is formed by the void channel. 10. The electronic device according to claim 9 , wherein the void channel has a rectangular, slit, circular or oval cross-sectional shape. 11. The electronic device according to claim 9 , wherein the sidewalls are on a mesa or pillar structure having a rectangular, slit, circular or oval cross-sectional. 12. The electronic device according to claim 5 , wherein a two-dimensional electron system enabled low-voltage electron emission from the two dimensional electron system is utilized for photodetection, wherein the first conducting layer comprises a transparent electrode. 13. The electronic device according to claim 5 , wherein a two-dimensional electron system enabled low-voltage electron emission from the two dimensional electron system is utilized for image sensing. 14. The electronic device according to claim 13 , wherein the image sensing is combined with color sensing structures. 15. The electronic device according to claim 5 , wherein a two-dimensional electron system enabled low-voltage electron emission from the two dimensional electron system is utilized for photovoltaic conversion without pn-junctions. 16. The electronic device according to claim 5 , wherein a two-dimensional electron system enabled low voltage emission from the two dimensional electron system is utilized as a low-voltage, stable electron source. 17. The electronic device according to claim 16 , wherein the stable low-voltage electron

Assignees

Inventors

Classifications

  • of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors · CPC title

  • Cold cathodes, e.g. field-emissive cathode · CPC title

  • microengineered, e.g. Spindt-type · CPC title

  • with microengineered cathode, e.g. Spindt-type · CPC title

  • H01J1/3046Primary

    Edge emitters · CPC title

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What does patent US9331189B2 cover?
An electronic device including a first conducting layer, a second conducting layer, and an insulating layer provided between the conducting layers. At least one side wall extends from the first conducting layer to the second conducting layer and includes at least a portion of the first conducting layer, the second conducting layer and the insulating layer. A bias voltage is applied between the …
Who is the assignee on this patent?
Univ Pittsburgh—Of The Commonwealth System Of Higher Education
What technology area does this patent fall under?
Primary CPC classification H01J1/3046. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 03 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).