Oxide-based resistive memory having a plasma-exposed bottom electrode

Patent metadata

Field	Value
Publication number	US-11647680-B2
Application number	US-202016898527-A
Country	US
Kind code	B2
Filing date	Jun 11, 2020
Priority date	Jun 11, 2020
Publication date	May 9, 2023
Grant date	May 9, 2023

Abstract

Provided are embodiments for a semiconductor device. The semiconductor device includes a bottom electrode, wherein the bottom electrode is formed on a metal interconnect electrode, and a dielectric layer on a surface of the bottom electrode. The semiconductor device also includes a top electrode formed on a surface of the dielectric layer, wherein at least one of the top electrode or the bottom electrode is a plasma treated top electrode or plasma treated bottom electrode. Also provided are embodiments for a method of fabricating a resistive switching device where at least one of the plurality of layers of the memory stack is processed with a charge particle treatment.

First claim

What is claimed is:

1. A method of fabricating a resistive switching device, the method comprising:
forming a metal interconnect electrode;
forming a memory stack comprising a plurality of layers, wherein the plurality of layers includes a top electrode, a bottom electrode, and a dielectric layer between the top electrode and the bottom electrode;
wherein forming the memory stack comprises forming a blanket bottom electrode layer then removing portions of the blanket bottom electrode layer; and
forming current-conducting filaments of the memory stack by performing a charge particle treatment on at least one of the plurality of layers of the memory stack while a portion of the blanket bottom electrode is exposed.

2. The method of claim 1 , wherein:
the metal interconnect electrode comprises a first size dimension;
the memory stack comprises a second size dimension and is formed on the metal interconnect electrode; and
a ratio of the second size dimension to the first size dimension is greater than 1000.

3. The method of claim 2 , wherein:
the metal interconnect electrode is formed on a surface of a metal interconnect layer; and
the metal interconnect layer is formed in an inter-level dielectric over a substrate.

4. The method of claim 1 , wherein a filament forming voltage of the memory stack is reduced by forming the current-conducting filaments of the memory stack by performing a charge particle treatment on at least one of the plurality of layers of the memory stack.

5. The method of claim 4 , further comprising:
etching the top electrode of the memory stack;
performing charge particle treatment on the top electrode of the memory stack; and
etching the dielectric layer and bottom electrode.

6. The method of claim 4 , further comprising:
etching the top electrode of the memory stack;
etching the dielectric layer; and
performing the charge particle treatment on the bottom electrode of the memory stack.

7. The method of claim 1 , wherein the bottom electrode, the dielectric layer, and the top electrode define a Resistive Random Access Memory (RRAM) device memory stack.

8. A method of fabricating a resistive switching device, the method comprising:
forming a bottom electrode, wherein forming the bottom electrode comprises forming a blanket bottom electrode layer then removing portions of the blanket bottom electrode layer;
forming a memory stack comprising a plurality of layers, wherein the plurality of layers includes a top electrode, the bottom electrode, and a dielectric layer between the top electrode and the bottom electrode;
forming current-conducting filaments of the memory stack by performing a charge particle treatment on at least one of the plurality of layers of the memory stack while a portion of the blanket bottom electrode is exposed; and
forming a spacer on a sidewall of at least a portion of the memory stack, wherein the spacer prevents a short between the top electrode and the bottom electrode while the portion of the blanket bottom electrode is exposed.

9. The method of claim 8 , wherein:
the memory stack is formed on a metal interconnect electrode;
the metal interconnect electrode comprises a first size dimension;
the memory stack comprises a second size dimension; and
a ratio of the second size dimension to the first size dimension is greater than 1000.

10. The method of claim 9 , wherein:
the metal interconnect electrode is formed on a surface of a metal interconnect layer; and
the metal interconnect layer is formed in an inter-level dielectric over a substrate.

11. The method of claim 8 , wherein a filament forming voltage of the memory stack is reduced by forming the current-conducting filaments of the memory stack by performing a charge particle treatment on at least one of the plurality of layers of the memory stack.

12. The method of claim 8 , further comprising:
etching the top electrode of the memory stack;
performing the charge particle treatment on the top electrode of the memory stack; and
etching the dielectric layer and bottom electrode.

13. The method of claim 8 , further comprising:
etching the top electrode of the memory stack;
etching the dielectric layer; and
performing the charge particle treatment on the bottom electrode of the memory stack.

Assignees

• IBM

Inventors

• Ando Takashi
• Miyazoe Hiroyuki
• Cartier Eduard Albert
• Khan Babar
• Kim Youngseok
• Kong Dexin
• Seo Soon-Cheon
• De Souza Joel P

Classifications

• H10N70/021

  Formation of switching materials, e.g. deposition of layers · CPC title

• H10N70/041 Primary

  Modification of switching materials after formation, e.g. doping (shaping H10N70/061) · CPC title

• H10N70/841

  Electrodes · CPC title

• H10N70/826

  adapted for essentially vertical current flow, e.g. sandwich or pillar type devices · CPC title

• H10B63/80 Primary

  Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays · CPC title