Source or drain structures with low resistivity

Patent metadata

Field	Value
Publication number	US-11621325-B2
Application number	US-201916368097-A
Country	US
Kind code	B2
Filing date	Mar 28, 2019
Priority date	Mar 28, 2019
Publication date	Apr 4, 2023
Grant date	Apr 4, 2023

Abstract

Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium and boron. The first and second source or drain structures have a resistivity less than or equal to 0.3 mOhm·cm.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a fin having a lower fin portion and an upper fin portion;
a gate stack over the upper fin portion of the fin, the gate stack having a first side opposite a second side;
a first source or drain structure comprising an epitaxial structure embedded in the fin at the first side of the gate stack;
a second source or drain structure comprising an epitaxial structure embedded in the fin at the second side of the gate stack, each epitaxial structure of the first and second source or drain structures in direct physical contact with the fin and comprising silicon, germanium and boron throughout an entirety of the epitaxial structure, with an atomic concentration of boron in the range of 1E20 atoms/cm 3 -3E21 atoms/cm 3 , and a germanium concentration in the range of 10% to 85%, and the first and second source or drain structures having a resistivity less than or equal to 0.3 mOhm·cm; and
an isolation structure laterally adjacent to one of the first source or drain structure or the second source or drain structure, wherein the one of the first source or drain structure or the second source or drain structure vertically overlaps the isolation structure.

2. The integrated circuit structure of claim 1 , wherein the resistivity of the first and second source or drain structures is in the range of 0.1 mOhm·cm to 0.3 mOhm·cm.

3. The integrated circuit structure of claim 1 , wherein the first and second source or drain structures induce a uniaxial compressive strain on the fin.

4. The integrated circuit structure of claim 1 , wherein the first and second source or drain structures are adjacent an isolation structure.

5. The integrated circuit structure of claim 4 , wherein the first and second source or drain structures have a lower surface below an upper surface of the isolation structure.

6. The integrated circuit structure of claim 1 , wherein the lower fin portion includes a portion of an underlying bulk single crystalline silicon substrate.

7. The integrated circuit structure of claim 1 , further comprising:
first and second dielectric gate sidewall spacers along the first and second sides of the gate stack, respectively.

8. The integrated circuit structure of claim 1 , further comprising:
a first conductive contact on the epitaxial structure of the first source or drain structure; and
a second conductive contact on the epitaxial structure of the second source or drain structure.

9. The integrated circuit structure of claim 8 , wherein the first and second conductive contacts are in a partial recess in the epitaxial structures of the first and second source or drain structures, respectively.

10. An integrated circuit structure, comprising:
a fin having a lower fin portion and an upper fin portion;
a gate stack over the upper fin portion of the fin, the gate stack having a first side opposite a second side;
a first source or drain structure comprising an epitaxial structure embedded in the fin at the first side of the gate stack, the epitaxial structure comprising a lower semiconductor layer and a capping semiconductor layer;
a second source or drain structure comprising an epitaxial structure embedded in the fin at the second side of the gate stack, the epitaxial structure comprising a lower semiconductor layer and a capping semiconductor layer, the lower semiconductor layer of each of the epitaxial structures of the first and second source or drain structures in direct physical contact with the fin and comprising silicon, germanium and boron throughout an entirety of the lower semiconductor layer of the epitaxial structure, the capping semiconductor layer of the epitaxial structure of each of the first and second source or drain structures having a germanium concentration greater than the lower semiconductor layer, and the first and second source or drain structures having a resistivity less than or equal to 0.3 mOhm·cm; and
an isolation structure laterally adjacent to one of the first source or drain structure or the second source or drain structure, wherein the one of the first source or drain structure or the second source or drain structure vertically overlaps the isolation structure.

11. The integrated circuit structure of claim 10 , wherein the lower semiconductor layer of each of the epitaxial structures of the first and second source or drain structures have an atomic concentration of boron in the range of 1E20 atoms/cm 3 -3E21 atoms/cm 3 , and a germanium concentration in the range of 10% to 85%.

12. The integrated circuit structure of claim 10 , wherein the resistivity of the first and second source or drain structures is in the range of 0.1 mOhm·cm to 0.3 mOhm·cm.

13. The integrated circuit structure of claim 10 , wherein the first and second source or drain structures induce a uniaxial compressive strain on the fin.

14. The integrated circuit structure of claim 10 , wherein the capping semiconductor layer consists essentially of germanium.

15. The integrated circuit structure of claim 10 , wherein the lower fin portion includes a portion of an underlying bulk single crystalline silicon substrate.

16. The integrated circuit structure of claim 10 , further comprising:
first and second dielectric gate sidewall spacers along the first and second sides of the gate stack, respectively.

17. The integrated circuit structure of claim 10 , further comprising:
a first conductive contact on the capping semiconductor layer of the first source or drain structure; and
a second conductive contact on the capping semiconductor layer of the second source or drain structure.

18. The integrated circuit structure of claim 17 , wherein the first and second conductive contacts are in a partial recess in the capping semiconductor layers of the first and second source or drain structures, respectively.

19. An integrated circuit structure, comprising:
a fin having a lower fin portion and an upper fin portion;
a gate stack over the upper fin portion of the fin, the gate stack having a first side opposite a second side;
a first source or drain structure comprising an epitaxial structure embedded in the fin at the first side of the gate stack, the epitaxial structure comprising a lower semiconductor layer and a capping semiconductor layer; and
a second source or drain structure comprising an epitaxial structure embedded in the fin at the second side of the gate stack, the epitaxial structure comprising a lower semiconductor layer and a capping semiconductor layer, the lower semiconductor layer of each of the epitaxial structures of the first and second source or drain structures in direct physical contact with the fin and comprising silicon, germanium and boron throughout an entirety of the lower semiconductor layer of the epitaxial structure, the capping semiconductor layer of the epitaxial structure of each of the first and second source or drain structures having a germanium concentration greater than the lower semiconductor layer, and the first and second source or drain structures having a resistivity less than or equal to 0.3 mOhm·cm;
an isolation structure laterally adjacent to one of the first source or drain structure or the second source or drain structure, wherein the one of the first source or drain structure or the second source or drain structure vertically overlaps the isolation structure;
a first conductive contact on the capping semiconductor layer of the first source or drain structure;
a second conductive contact on the capping semiconductor layer of the seco

Assignees

• Intel Corp

Inventors

• Bomberger Cory
• Murthy Anand
• Vishwanath Suresh

Classifications

• H10P14/3411 Primary

  Silicon, silicon germanium or germanium · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/073

  of die-attach connectors · CPC title