Source/Drain Feature to Contact Interfaces

Patent metadata

Field	Value
Publication number	US-2020135874-A1
Application number	US-201916276833-A
Country	US
Kind code	A1
Filing date	Feb 15, 2019
Priority date	Oct 26, 2018
Publication date	Apr 30, 2020
Grant date	—

Abstract

Examples of an integrated circuit with an interface between a source/drain feature and a contact and examples of a method for forming the integrated circuit are provided herein. In some examples, a substrate is received having a source/drain feature disposed on the substrate. The source/drain feature includes a first semiconductor element and a second semiconductor element. The first semiconductor element of the source/drain feature is oxidized to produce an oxide of the first semiconductor element on the source/drain feature and a region of the source/drain feature with a greater concentration of the second semiconductor element than a remainder of the source/drain feature. The oxide of the first semiconductor element is removed, and a contact is formed that is electrically coupled to the source/drain feature. In some such embodiments, the first semiconductor element includes silicon and the second semiconductor element includes germanium.

First claim

What is claimed is:

1 . A method comprising:
receiving a substrate having a source/drain feature disposed thereupon, wherein the source/drain feature includes a first semiconductor element and a second semiconductor element; oxidizing the first semiconductor element of the source/drain feature to produce an oxide layer that includes the first semiconductor element on the source/drain feature and a region of the source/drain feature with a greater concentration of the second semiconductor element than a remainder of the source/drain feature; removing the oxide layer; and forming a contact electrically coupled to the source/drain feature.

2 . The method of claim 1 , wherein the first semiconductor element includes silicon and the second semiconductor element includes germanium.

3 . The method of claim 2 further comprising introducing metal to the region of the source/drain feature to form a germanide layer of the source/drain feature.

4 . The method of claim 3 further comprising introducing nitrogen to the germanide layer to form a nitridized cap layer on a remainder of the germanide layer, wherein the contact physically couples to the nitridized cap layer.

5 . The method of claim 1 , wherein the region of the source/drain feature is substantially free of the first semiconductor element.

6 . The method of claim 1 , wherein:
the source/drain feature is a pFET source/drain feature; the substrate further has an nFET source/drain feature disposed thereupon that includes the first semiconductor element; the oxidizing of the first semiconductor element of the pFET source/drain feature further forms the oxide layer on the nFET source/drain feature; and the removing of the oxide layer removes the oxide layer from the pFET source/drain feature and the nFET source/drain feature.

7 . The method of claim 6 , wherein the nFET source/drain feature is substantially free of the second semiconductor element.

8 . The method of claim 1 , wherein:
the substrate further includes an inter-level dielectric disposed on the source/drain feature; the method further comprises forming a recess in the inter-level dielectric that exposes the source/drain feature; and the oxidizing and the removing of the oxide layer are performed through the recess.

9 . The method of claim 8 , wherein the contact is formed in the recess.

10 . A method comprising:
receiving a substrate having an nFET region with an nFET source/drain feature and a pFET region with a pFET source/drain feature, wherein the pFET source/drain feature includes a first semiconductor material and a second semiconductor material; performing an oxidation process on the nFET source/drain feature and the pFET source/drain feature to form an oxide layer on the nFET source/drain feature and on the pFET source/drain feature, wherein the oxidation process further forms a region of the pFET source/drain feature with a greater concentration of the second semiconductor material than a remainder of the pFET source/drain feature; removing the oxide layer from the nFET source/drain feature and from the pFET source/drain feature; and forming a first contact electrically coupled to the nFET source/drain feature and a second contact electrically coupled to the pFET source/drain feature.

11 . The method of claim 10 , wherein the first semiconductor material includes silicon and the second semiconductor material includes germanium.

12 . The method of claim 11 , wherein the nFET source/drain feature is substantially free of germanium.

13 . The method of claim 11 further comprising forming a germanide layer from the region of the pFET source/drain feature with the greater concentration of the second semiconductor material.

14 . The method of claim 10 , wherein the region of the pFET source/drain feature is substantially free of the first semiconductor material.

15 . The method of claim 10 , wherein:
the substrate further includes an inter-level dielectric disposed on the nFET source/drain feature and on the pFET source/drain feature; the method further comprises forming a first recess in the inter-level dielectric that exposes the nFET source/drain feature and a second recess in the inter-level dielectric that exposes the pFET source/drain feature; and the performing of the oxidation process and the removing of the oxide layer are performed through the first recess and the second recess.

16 . A device comprising:
a substrate having a fin extending from a remainder of the substrate; a source/drain feature disposed on the fin, wherein the source/drain feature includes a SiGe semiconductor, and wherein a top portion of the source/drain feature has a different germanium concentration than a bottom portion of the source/drain feature; and a contact coupling to the top portion of the source/drain feature.

17 . The device of claim 16 further comprising a dielectric layer disposed on the top portion of the source/drain feature, wherein the dielectric layer includes silicon oxide, and wherein the contact extends through the dielectric layer.

18 . The device of claim 17 further comprising an etch stop layer disposed on the dielectric layer, wherein the contact extends through the etch stop layer.

19 . The device of claim 17 , wherein the dielectric layer includes a side portion that slopes upward.

20 . The device of claim 19 , wherein the dielectric layer includes a horizontal central portion extending from the side portion that physically contacts the contact.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Shih Ding-Kang
• Wang Sung-Li
• Tsai Pang-Yen

Classifications

• H01L29/7848

  Electricity · mapped topic

• H01L29/0847

  Electricity · mapped topic

• H01L21/02532

  Electricity · mapped topic

• H01L29/7831

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic