Semiconductor devices and methods of manufacturing semiconductor devices

Patent metadata

Field	Value
Publication number	US-2018096934-A1
Application number	US-201715493965-A
Country	US
Kind code	A1
Filing date	Apr 21, 2017
Priority date	Oct 5, 2016
Publication date	Apr 5, 2018
Grant date	—

Abstract

A semiconductor device includes a substrate having an active region, a gate structure disposed on the active region, a source/drain region disposed in the active region at a side of the gate structure, a first interlayer insulating layer and a second interlayer insulating layer sequentially disposed on the gate structure and the source/drain region, a first contact plug connected to the source/drain region through the first interlayer insulating layer, a second contact plug connected to the gate structure through the first interlayer insulating layer and the second interlayer insulating layer, a first metal line disposed on the second interlayer insulating layer, and having a metal via disposed in the second interlayer insulating layer and connected to the first contact plug, and a second metal line disposed on the second interlayer insulating layer, and directly connected to the second contact plug. An interval between the first contact plug and the second contact plug may be about 10 nm or less.

First claim

1 . A semiconductor device comprising:
a substrate having an active region; a gate structure disposed on the active region; a source/drain region disposed in the active region at a side of the gate structure; a first interlayer insulating layer and a second interlayer insulating layer sequentially disposed on the gate structure and the source/drain region; a first contact plug connected to the source/drain region through the first interlayer insulating layer; a second contact plug connected to the gate structure through the first interlayer insulating layer and the second interlayer insulating layer; a first metal line disposed on the second interlayer insulating layer, and having a metal via disposed in the second interlayer insulating layer and connected to the first contact plug; and a second metal line disposed on the second interlayer insulating layer, and directly connected to the second contact plug.

2 . The semiconductor device of claim 1 , further comprising: an etch stop layer disposed between the first interlayer insulating layer and the second interlayer insulating layer.

3 . The semiconductor device of claim 2 , wherein the etch stop layer comprises aluminum nitride (AlN).

4 . The semiconductor device of claim 1 , wherein the first contact plug comprises a metal silicide layer connected to the source/drain region.

5 . The semiconductor device of claim 1 , wherein the first contact plug and the second contact plug each comprises tungsten (W), cobalt (Co), an alloy thereof, or a combination thereof.

6 . The semiconductor device of claim 1 , wherein each of the first contact plug and the second contact plug comprises a conductive barrier layer disposed on lateral surfaces and a lower surface thereof.

7 . (canceled)

8 . The semiconductor device of claim 1 , further comprising: a spacer disposed along lateral surfaces of each of the first contact plug and the second contact plug.

9 . (canceled)

10 . The semiconductor device of claim 1 , wherein an interval between the first contact plug and the second contact plug is about 10 nm or less.

11 . The semiconductor device of claim 1 , wherein the first metal line and the second metal line each comprises copper (Cu) or a copper-containing alloy.

12 . The semiconductor device of claim 1 , wherein the first metal line and the metal via are integrated with each other.

13 . The semiconductor device of claim 1 , wherein the active region has a fin-type active region protruding upwardly from the substrate and extending in a first direction, and the gate structure is disposed and extending in a second direction intersecting the fin-type active region in the first direction, and the source/drain region is formed in the fin-type active region at one side of the gate structure.

14 . The semiconductor device of claim 13 , wherein the fin-type active region is provided as a plurality of fin-type active regions, and the source/drain region is merged with one or more source/drain regions adjacent thereto.

15 . The semiconductor device of claim 14 , wherein the second contact plug is formed over the merged source/drain regions to have a bar shape.

16 . A semiconductor device comprising:
a substrate; a gate structure disposed on the substrate; a source/drain region disposed at a side of the gate structure; a first contact plug connected to the source/drain region, and formed in a substantially vertical direction from an upper surface of the substrate; a second contact plug connected to the gate structure, and formed in a substantially vertical direction from the upper surface of the substrate; and a first metal line and a second metal line connected to the first contact plug and the second contact plug, respectively, and disposed on a first level, wherein an upper surface of one of the first contact plug and the second contact plug is disposed on the first level and directly connected to one of the first metal line and the second metal line, and an upper surface of the other one of the first contact plug and the second contact plug is disposed on a second level, lower than the first level, and connected to the other one of the first metal line and the second metal line by a metal via.

17 . The semiconductor device of claim 16 , wherein the upper surface of the first contact plug is disposed on the first level and directly connected to the first metal line, and the upper surface of the second contact plug is disposed on the second level and connected to the second metal line by the metal via.

18 . The semiconductor device of claim 16 , wherein the upper surface of the second contact plug is disposed on the first level and directly connected to the second metal line, and the upper surface of the first contact plug is disposed on the second level and connected to the first metal line by the metal via.

19 . The semiconductor device of claim 16 , further comprising:
an interlayer insulating layer disposed on the substrate to cover the gate structure and the source/drain region, and having an upper surface disposed on the first level; and an etch stop layer disposed on the second level within the interlayer insulating layer.

20 . The semiconductor device of claim 16 , wherein the first contact plug and the second contact plug each comprises tungsten (W), cobalt (Co), an alloy thereof, or a combination thereof, and the first metal line, the second metal line, and the metal via each comprises copper (Cu) or a copper-containing alloy.

21 . The semiconductor device of claim 20 , wherein each of the first contact plug and the second contact plug comprises a conductive barrier layer disposed on lateral surfaces and a lower surface thereof and including at least one of titanium nitride (TiN), Tantalum nitride (TaN), aluminum nitride (AlN), tungsten nitride (WN), and combinations thereof.

22 . (canceled)

23 . A semiconductor device comprising:
a substrate; a gate structure and a source/drain region disposed on the substrate; a first interlayer insulating layer disposed over the gate structure and the source/drain region; a first contact plug disposed in the first interlayer insulating layer to connect the source/drain region, with a top surface of the first contact plug and a top surface of the first interlayer insulating layer being at a first level; a second interlayer insulating layer disposed on the first interlayer insulating layer; a second contact plug disposed in the first and second interlayer insulating layers to connect the gate structure, with a top surface of the second contact plug and a top surface of the second interlayer insulating layer being at a second level, higher than the first level; a first metal line disposed on the second interlayer insulating layer, the first metal line including a metal via disposed in the second interlayer insulating layer to connect the first contact plug, with a top surface of the metal via being at the second level; and a second metal line disposed on the second interlayer insulating layer to directly connect the second contact plug at the second level.

24 . (canceled)

Assignees

• Samsung Electronics Co Ltd

Inventors

• Siew Yong Kong
• Tseng Wei Hsiung
• Kim Changhwa

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/084 Primary

  for dual-damascene structures · CPC title