Memory device skipping refresh operation and operation method thereof

Patent metadata

Field	Value
Publication number	US-11610624-B2
Application number	US-202117474666-A
Country	US
Kind code	B2
Filing date	Sep 14, 2021
Priority date	Feb 4, 2021
Publication date	Mar 21, 2023
Grant date	Mar 21, 2023

Abstract

Provided are a memory device skipping a refresh operation and an operating method thereof. The memory device includes a memory cell array including N rows; a refresh controller configured to control a refresh operation for the N rows of the memory cell array based on a refresh command; and an access information storage circuit including a plurality of registers configured to store flag information corresponding to each of the N rows, wherein a first value indicates rows that have been accessed, and a second value indicates rows that have not been accessed. The refresh controller is further configured to control whether the refresh operation is performed for a first row of the N rows at a refresh timing for the first row based on the flag information corresponding to the first row.

First claim

What is claimed is:

1. A memory device comprising:
a memory cell array comprising N rows, wherein N is an integer greater than or equal to 2;
a refresh controller configured to control a refresh operation for the N rows of the memory cell array based on a refresh command; and
an access information storage circuit comprising a plurality of registers configured to store flag information corresponding to each of the N rows, wherein a first value indicates rows that have been accessed, and a second value indicates rows that have not been accessed,
wherein the refresh controller is further configured to, at a refresh timing for a first row of the N rows:
obtain a refresh address indicating the first row,
obtain the flag information corresponding to the first row from the access information storage circuit based on the refresh address,
based on the refresh address indicating the first row and the flag information corresponding to the first row having the first value, control the refresh operation for the first row to be skipped, and
based on the refresh address indicating the first row and the flag information corresponding to the first row having the second value, control the refresh operation for the first row to be performed.

2. The memory device of claim 1 , further comprising a control logic configured to:
control access to the memory cell array based on a command and an address received from a host; and
identify a row to which access is performed based on the address received from the host, and set the flag information corresponding to the identified row as the first value.

3. The memory device of claim 2 , wherein the control logic is further configured to control a mode setter to set an operation mode related to the refresh operation, and
wherein the refresh controller is further configured to:
based on the operation mode being a refresh skip mode and the first row having been previously accessed in a first refresh period, control the refresh operation of the first row to be skipped at the refresh timing for the first row in the first refresh period, and
based on the operation mode being a refresh performing mode, control the refresh operation of the first row to be performed at the refresh timing for the first row in the first refresh period regardless of whether the first row has been accessed in the first refresh period.

4. The memory device of claim 3 , wherein the refresh controller is further configured to, based on the operation mode being a refresh performing mode of other rows and the first row having been previously accessed in the first refresh period, control the refresh operation to be performed on a second row of the N rows other than the first row at the refresh timing for the first row in the first refresh period.

5. The memory device of claim 4 , further comprising a weak row information storage circuit configured to store information indicating one or more rows having relatively poor data retention characteristics among the N rows,
wherein the refresh controller is further configured to identify the second row based on the information stored in the weak row information storage circuit indicating the second row.

6. The memory device of claim 1 , wherein the refresh controller is further configured to, after the refresh operation for the first row is skipped based on the flag information corresponding to the first row having the first value, reset the flag information corresponding to the first row to the second value at the refresh timing for the first row.

7. The memory device of claim 1 , wherein the refresh controller is further configured to:
in a first refresh period, based on the flag information corresponding to at least two rows among the N rows having the first value, control the refresh operation of the at least two rows to be skipped in the first refresh period, and
reset the flag information of the plurality of registers of the access information storage circuit to the second value at an end of the first refresh period.

8. The memory device of claim 1 , wherein the memory device is configured to transmit skip information indicating that the refresh operation for one or more rows among the N rows has been skipped to a host through at least one terminal.

9. The memory device of claim 8 , wherein the memory device is further configured to receive any one or any combination of a first parameter and a second parameter related to the refresh operation from the host, and
wherein the refresh controller is further configured to control a reception interval of the refresh command based on the first parameter.

10. The memory device of claim 9 , wherein the refresh controller is further configured to control a time to perform the refresh operation in response to one refresh command received from the host based on the second parameter.

11. The memory device of claim 1 , wherein the memory device is further configured to operation in M refresh modes, wherein M is an integer greater than or equal to 2, and
wherein a maximum of M−1 refresh operations are skipped in each of the N rows in a first refresh period based on the memory device operating in an Mth refresh mode from among the M refresh modes.

12. An operating method of a memory device, the operating method comprising:
accessing a first row from among N rows provided in a memory cell array, wherein N is an integer greater than or equal to 2;
storing flag information having a first value in a first register corresponding to the first row in an access information storage circuit comprising a plurality of registers;
generating a refresh address indicating the first row;
obtaining the flag information corresponding to the first row from the access information storage circuit based on the refresh address;
identifying the flag information stored in the first register corresponding to the first row at a refresh timing for the first row based on a refresh command and the refresh address; and
skipping a refresh operation for the first row based on the refresh address indicating the first row and the flag information corresponding to the first row having the first value.

13. The operating method of claim 12 , further comprising:
identifying the flag information stored in a second register corresponding to a second row in the access information storage circuit at a refresh timing for the second row based on the refresh command; and
performing the refresh operation on the second row based on the flag information corresponding to the second row having a second value.

14. The operating method of claim 12 , further comprising after skipping the refresh operation for the first row, resetting the flag information stored in the first register to a second value.

15. The operating method of claim 12 , further comprising performing the refresh operation on a second row different from the first row at the refresh timing for the first row according to an operation mode set in the memory device.

16. The operating method of claim 12 , further comprising transmitting, by the memory device, skip information indicating that the refresh operation for one or more rows among the N rows has been skipped to a host through at least one terminal.

17. The operating method of claim 16 , further comprising:
receiving the refresh command from the host every first time interval based on a first parameter indicating the first time interval in a first refresh period; and
receiving the refresh command from the host every second time interval different from the first time interval based on the first parameter indi

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Minsu
• Kim Namhyung
• Kim Daejeong
• Kim Dohan
• Park Chanik
• Seo Deokho
• Shin Wonjae
• Lee Changmin
• Jung Ilguy
• CHOI Insu

Classifications

• G11C11/4063

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing · CPC title

• G11C11/40615 Primary

  Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G11C11/40611 Primary

  External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh · CPC title

• G11C2211/4065

  Low level details of refresh operations · CPC title