Memory device and refresh method thereof

Patent metadata

Field	Value
Publication number	US-10529406-B2
Application number	US-201715823152-A
Country	US
Kind code	B2
Filing date	Nov 27, 2017
Priority date	Jan 9, 2017
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

A memory device includes a memory cell array that includes a plurality of memory cell rows, a temperature sensor that detects a temperature of the memory cell array and generates internal temperature data, a first register that stores external temperature data received from outside of the memory device, and a refresh control unit that determines a skip ratio of refresh commands received at a refresh frequency that corresponds to the external temperature data by comparing the internal temperature data and the external temperature data and performing a refresh operation for the plurality of memory cell rows in response to refresh commands skipped and transmitted based on the skip ratio.

First claim

What is claimed is:

1. A method of refreshing a memory device that includes a memory cell array that includes a plurality of memory cell rows, the method comprising:
storing external temperature data received from a memory controller;
determining a refresh period that corresponds to the external temperature data; and
outputting a plurality of memory cell row addresses or at least one weak cell row address of the plurality of memory cell row addresses based on a ratio that corresponds to the refresh period, in response to a refresh command received from the memory controller, wherein weak cell rows of the memory cell array have a shorter data retention time than normal cell rows of the memory cell array.

2. The refresh method of claim 1 , wherein:
outputting the plurality of memory cell row addresses or at least one weak cell row address includes outputting the plurality of memory cell row addresses by increasing a ratio of outputting normal memory cell row addresses and weak memory cell row addresses, when the refresh period is decreased.

3. The refresh method of claim 1 , further comprising:
detecting internal temperature data;
comparing the internal temperature data and the external temperature data; and
determining a skip ratio of the received refresh command based on the comparison result.

4. The refresh method of claim 3 , wherein:
outputting the plurality of memory cell row addresses or the at least one weak cell row address includes skipping executing a refresh command for the plurality of memory cell row addresses based on the skip ratio.

5. The refresh method of claim 3 , wherein:
determining the skip ratio of the input refresh command based on the comparison result includes
determining the skip degree to skip executing the received refresh command when the temperature section of the internal temperature data is in the temperature section of the external temperature data, and
determining the skip ratio so as to execute the received refresh command when the temperature section of the internal temperature data deviates from the temperature section of the external temperature data.

6. The refresh method of claim 1 , further comprising:
receiving a mode register read command from the memory controller; and
transmitting output temperature data that increases the internal temperature data to the memory controller.

7. A memory device, comprising:
a memory cell array that includes a plurality of memory cell rows;
a temperature sensor that detects a temperature of the memory cell array and generates internal temperature data;
a first register that stores external temperature data received from outside the memory device; and
a refresh control unit that determines a skip ratio of refresh commands received at a refresh frequency that corresponds to the external temperature data by comparing the internal temperature data and the external temperature data and performing a refresh operation for the plurality of memory cell rows in response to refresh commands skipped and transmitted based on the skip ratio,
wherein the refresh control unit performs a refresh operation for at least one weak cell row of the plurality of memory cell rows in response to at least one first refresh command of the received refresh commands, wherein weak cell rows of the plurality of memory cell rows have a shorter data retention time than normal cells of the plurality of memory cell rows.

8. The memory device of claim 1 , wherein:
the refresh control unit skips second refresh commands of the received refresh commands based on the skip ratio, except for at least one first refresh command of the received input refresh commands.

9. The memory device of claim 8 , wherein:
the refresh control unit performs a refresh operation for at least one weak cell row by reducing a ratio of the first refresh commands to the second refresh commands when a refresh period is increased.

10. The memory device of claim 1 , wherein:
the refresh control unit increases the skip ratio when a value of the internal temperature data is reduced while the value of the external temperature data remains constant.

11. The memory device of claim 1 , wherein:
the temperature sensor generates a value that corresponds to a temperature section of a plurality of divided temperature sections that includes the temperature as the internal temperature data.

12. The memory device of claim 11 , wherein:
the refresh control unit determines the skip ratio when the temperature section of the internal temperature data is in the temperature section of the external temperature data.

13. The memory device of claim 11 , wherein:
the refresh control unit does not skip the input refresh command when the temperature section of the internal temperature data deviates from the temperature section of the external temperature data.

14. The memory device of claim 11 , further comprising:
a second register that stores output temperature data that increases the value of the internal temperature data; and
a data pad that transmits the output temperature data out of the memory device.

15. The memory device of claim 14 , wherein:
the output temperature data is transmitted through the data pad in response to a mode register read command received from outside the memory device and the external temperature data is received through the data pad in response to a mode register write command received from outside the memory device.

16. The memory device of claim 15 , wherein:
the internal temperature data and the external temperature data each have a different number of bits and the external temperature data and the output temperature data have a same number of bits.

17. A memory system, comprising:
a plurality of memory devices, each including a memory cell array that includes a plurality of memory cell rows and a temperature sensor, wherein the temperature sensors of each of the plurality of memory devices generate a plurality of internal temperature data by detecting a temperature of the memory cell array of each of the plurality of memory devices; and
a memory controller that receives the internal temperature data from the plurality of memory devices and outputs a refresh command for refreshing the plurality of memory cell rows to the plurality of memory devices at a frequency that corresponds to a highest temperature of the plurality of internal temperature data,
wherein a refresh operation is performed for at least one weak cell row of the plurality of memory cell rows in response to at least one first refresh command of the outputted refresh commands, wherein weak cell rows of the plurality of memory cell rows have a shorter data retention time than normal cells of the plurality of memory cell rows.

18. The memory system of claim 17 , wherein:
the memory controller outputs reference temperature data of the highest temperature of the internal temperature data to the plurality of memory devices, and
the plurality of memory devices selectively skip the refresh command based on a result of comparing the reference temperature data and the internal temperature data.

19. The memory system of claim 18 , wherein:
at least one of the plurality of memory devices does not skip the refresh command.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Won Jun
• Yang Hui Kap

Classifications

• G11C11/40615

  Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs · CPC title

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title

• G11C11/40626 Primary

  Temperature related aspects of refresh operations · CPC title

• G11C14/0009

  in which the volatile element is a DRAM cell · CPC title

• G11C11/40611

  External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh · CPC title