Techniques for reducing row hammer refresh

Patent metadata

Field	Value
Publication number	US-10790005-B1
Application number	US-201916396132-A
Country	US
Kind code	B1
Filing date	Apr 26, 2019
Priority date	Apr 26, 2019
Publication date	Sep 29, 2020
Grant date	Sep 29, 2020

Abstract

Methods, systems, and devices for techniques for reducing row hammer refresh are described. A memory device may be segmented into regions based on bits (e.g., the least significant bits) of row addresses such that consecutive word lines belong to different regions. A memory device may initiate a refresh operation for a first row of memory cells corresponding to a first word line. The memory device may determine that the first row is an aggressor row of a row hammer attack and may determine an adjacent row associated with a second word line as a victim row that may need to be refreshed (e.g., to counteract potential data corruption due to a row hammer attack). The memory die may determine whether to perform a row-hammer refresh operation on the victim row based on whether the victim row belongs to a region that is masked.

First claim

What is claimed is:

1. A method comprising:
identifying a first word line indicated by a command for a first refresh operation;
identifying a masking region associated with a second word line adjacent to the first word line based at least in part on identifying the first word line;
determining, based at least in part on identifying the masking region, a mask indicator associated with the masking region, wherein the mask indicator indicates whether data is stored in the masking region; and
performing a second refresh operation on memory cells coupled with the second word line based at least in part on determining the mask indicator.

2. The method of claim 1 , further comprising:
identifying a first address associated with the first word line based at least in part on a counter value, wherein identifying the first word line is based at least in part on the first address; and
identifying a second address associated with the second word line based at least in part on the first address, wherein determining the mask indicator is based at least in part on identifying the second address.

3. The method of claim 2 , wherein identifying the mask indicator associated with the second word line comprises:
identifying the mask indicator based at least in part on a plurality of least significant bits of the second address.

4. The method of claim 2 , further comprising: receiving, from a host device, the command that indicates the first refresh operation is to be performed; and identifying the counter value based at least in part on receiving the command.

5. The method of claim 4 , wherein the second refresh operation is performed based at least in part on receiving the command.

6. The method of claim 2 , wherein the second address is consecutive with the first address.

7. The method of claim 1 , further comprising:
identifying, based at least in part a plurality of least significant bits of an address of the first word line, a second mask indicator of a second masking region associated with the first word line, wherein the second mask indicator indicates whether data is stored in the second masking region; and
refraining from performing the first refresh operation on memory cells coupled with the first word line based at least in part on the second mask indicator.

8. The method of claim 1 , further comprising:
performing the first refresh operation on memory cells coupled with the first word line, wherein identifying the masking region associated with the second word line is based at least in part on performing the first refresh operation.

9. The method of claim 1 , wherein the first word line and the second word line are included in a set of word lines associated with an array of memory cells that is segmented into a plurality of regions, each region associated with a plurality of non-adjacent word lines of the set of word lines and with a respective mask indicator.

10. The method of claim 1 , further comprising:
determining, based at least in part on a plurality of access operations performed on memory cells coupled with the first word line, that the second word line receives interference based at least in part on the plurality of access operations being performed on memory cells coupled with the first word line, wherein the determining the mask indicator is based at least in part on determining that the second word line is a victim word line.

11. The method of claim 1 , further comprising:
identifying a third word line adjacent to the second word line based at least in part on identifying the first word line, wherein the second word line is between the first word line and the third word line;
determining, based at least in part on identifying the third word line, a third mask indicator of a third masking region associated with the third word line, wherein the third mask indicator indicates whether data is stored in the third masking region; and
performing a third refresh operation on memory cells coupled with the third word line based at least in part on the third mask indicator.

12. The method of claim 11 , wherein the second refresh operation and the third refresh operation comprise row hammer refresh operations.

Assignees

• Micron Technology Inc

Inventors

• He Yuan
• Ito Yutaka

Classifications

• G11C11/4078

  Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells (protection of memory contents during checking or testing G11C29/52) · CPC title

• G11C11/4085

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title

• G11C11/40615 Primary

  Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs · CPC title

• G11C2211/4065

  Low level details of refresh operations · CPC title

• G11C11/4087

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title