Memroy device and operating method thereof

Patent metadata

Field	Value
Publication number	US-2018166117-A1
Application number	US-201715681595-A
Country	US
Kind code	A1
Filing date	Aug 21, 2017
Priority date	Dec 14, 2016
Publication date	Jun 14, 2018
Grant date	—

Abstract

An operating method of a memory device including a plurality of memory cells may include: measuring data retention times of at least a portion of the plurality of memory cells; and optimizing a refresh operation on the plurality of memory cells using the measurement result.

First claim

What is claimed is:

1 . An operating method of a memory device including a plurality of memory cells, comprising:
measuring data retention times of at least a portion of the plurality of memory cells; and optimizing a refresh operation on the plurality of memory cells using the measurement result.

2 . The operating method of claim 1 , further comprising storing the measurement result of the data retention times of the plurality of memory cells.

3 . The operating method of claim 1 , wherein the measuring of the data retention times comprises:
writing test data to the plurality of memory cells; skipping a refresh operation on one or more test cells among the plurality of memory cells by a preset number of times; and detecting the data retention times of the test cells by comparing the test data to data of the test cells.

4 . The operating method of claim 1 , wherein the measuring of the data retention times comprises:
a first detection step of detecting a cell group of which the data retention time is less than a reference time, among two or more cell groups, wherein the cell group comprises memory cells included in two or more rows, among the plurality of memory cells; and a second detection step of detecting a sub cell group of which the data retention time is less than the reference time, among two or more sub cell groups included in the cell group detected at the first detection step, wherein the sub cell group comprises memory cells included in one or more rows of the two or more rows included in the cell group detected at the first detection step.

5 . The operating method of claim 2 , wherein the storing of the measurement result comprises:
storing the measurement result in a nonvolatile memory, a plurality of dummy cells, a plurality of latches or a plurality of fuses.

6 . The operating method of claim 5 , wherein the optimizing of the refresh operation comprises:
reading the measurement result stored in the nonvolatile memory, the plurality of dummy cells or the plurality of latches; and adjusting a refresh cycle of the memory cell according to the measurement result.

7 . The operating method of claim 1 , wherein the optimizing of the refresh operation comprises:
detecting one or more weak cells having a shorter data retention time than a reference time, based on the measurement result, among the plurality of memory cells; optimizing the refresh operation by increasing the data retention time of the weak cells or correcting data of the weak cells, and increasing a refresh cycle of the weak cell.

8 . The operating method of claim 1 , wherein the optimizing of the refresh operation comprises:
detecting one or more weak cells having a shorter data retention time than a first reference time, and detecting one or more strong cells having a longer data retention time than a second reference time, based on the measurement result, among the plurality of memory cells; and minimizing a refresh frequency by decreasing a refresh cycle of the weak cells and increasing a refresh cycle of the strong cells.

9 . The operating method of claim 1 , wherein the measurement result includes an address of a weak cell or one-bit data indicating whether each memory cell is a weak cell.

10 . A memory device comprising:
a plurality of memory cells; a test control unit suitable for measuring data retention times of the plurality of memory cells; and a refresh control unit suitable for controlling a refresh operation on the plurality of memory cells to be optimized, using the measurement result of the test control unit.

11 . The memory device of claim 10 , wherein the test control unit
writes test data to the plurality of memory cells, skips a refresh operation on one or more test cells among the plurality of memory cells by a preset number of times, and detects the data retention times of the test cells by comparing the test data and data of the test cells.

12 . The memory device of claim 10 , wherein the test control unit
detects a cell group of which the data retention time is less than a reference time, among two or more cell groups, and detects a sub cell group of which the data retention time is less that the reference time, among two or more sub cell groups included in the detected cell group, wherein the cell group comprises memory cells included in two or more rows among the plurality of memory cells and the sub cell group comprises memory cells included in one or more rows of two or more rows included in the cell group.

13 . The memory device of claim 10 , further comprising a result storage unit suitable for storing the measurement result of the test control unit.

14 . The memory device of claim 13 , wherein the result storage unit comprising a nonvolatile memory, a plurality of dummy cell, a plurality of latches or a plurality of fuses.

15 . The memory device of claim 13 , wherein the refresh control unit adjusts a refresh cycle of the memory cell by referring to the measurement result stored in the result storage unit.

16 . The memory device of claim 10 , wherein the refresh control unit
detects one or more weak cells having a shorter data retention time than a reference time, based on the measurement result, among the plurality of memory cells, and optimizes the refresh operation by increasing the data retention time of the weak cells or correcting data of the weak cells, and increasing a refresh cycle of the weak cell.

17 . The memory device of claim 10 , wherein the refresh control unit
detects one or more weak cells having a shorter data retention time than a first reference time, and detects one or more strong cells having a longer data retention time than a second reference time, based on the measurement result, among the plurality of memory cells, and optimizes the refresh operation by decreasing a refresh cycle of the weak cells and increasing a refresh cycle of the strong cells.

18 . The memory device of claim 10 , further comprising:
a temperature measurement unit suitable for measuring a temperature at which the plurality of memory cells operate.

19 . The memory device of claim 18 , wherein the refresh control unit increases a refresh frequency as the temperature measured by the temperature measurement unit rises, and decreases the refresh frequency as the temperature measured by the temperature measurement unit falls.

20 . The memory device of claim 10 , wherein the measurement result includes an address of a weak cell or one-bit data indicating whether each memory cell is a weak cell.

Assignees

• Sk Hynix Inc

Inventors

• Choi Hae-Rang
• Kim Youk-Hee
• Lee Jae-Seung
• JO Mi-Hyeon
• Lee Dong-Jae
• Kang Kyeong-Pil
• Chi Sung-Soo
• Won Hyung-Sik
• Jung Hun-Sam
• Lee Yo-Sep

Classifications

• G11C29/023

  in clock generator or timing circuitry · CPC title

• G11C29/40

  using compression techniques · CPC title

• G11C11/40611

  External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh · CPC title

• G11C11/4045 Primary

  using a plurality of serially connected access transistors, each having a storage capacitor · CPC title

• G11C2211/4068

  Voltage or leakage in refresh operations · CPC title