Methods and systems for controlling refresh operations of a memory device

Patent metadata

Field	Value
Publication number	US-11195568-B1
Application number	US-202017060913-A
Country	US
Kind code	B1
Filing date	Oct 1, 2020
Priority date	Aug 12, 2020
Publication date	Dec 7, 2021
Grant date	Dec 7, 2021

Abstract

Methods and systems for controlling refresh operations of a memory device. A method disclosed herein includes receiving, by a refresh controller of the memory device, a refresh command from a host for performing the refresh operation on a plurality of memory rows. The method further includes selecting, by the refresh controller, at least one memory row from the plurality of memory rows for the refresh operation using a refresh-row selection circuitry. The at least one memory row is selected by performing digital reading or analog reading of at least one row condition cell (RCC) and at least one supplemental cell that are connected to each memory row of the memory rows. The method further includes performing, by the refresh controller, the refresh operation on the selected at least one memory row.

First claim

What is claimed is:

1. A method for controlling a refresh operation of a memory device, the method comprising:
receiving, by a refresh controller from a host, at least one refresh command for a plurality of memory rows in the memory device, wherein each of the plurality of memory rows include a plurality of memory cells;
selecting, by a refresh-row selection circuitry, at least one memory row from the plurality of memory rows by reading at least one row condition cell (RCC) and at least one supplemental cell, each of the at least one RCC and the at least one supplemental cell being associated with respective memory rows of the plurality of memory rows; and
performing, by the refresh controller, the refresh operation on the selected at least one memory row using a refresh circuitry.

2. A method for controlling a refresh operation of a memory device, the method comprising:
receiving, by a refresh controller, from a host, at least one refresh command for a plurality of memory rows in the memory device, wherein a plurality of memory cells are on each memory row;
selecting, by a refresh-row selection circuitry, at least one memory row from the plurality of memory rows based on at least one condition and refresh rules of the plurality of memory cells, the at least one condition and the refresh rules determined by reading at least one row condition cell (RCC) and at least one supplemental cell, each RCC and each supplemental cell being associated with a memory row of the plurality of memory rows;
performing, by the refresh controller, the refresh operation on the selected at least one memory row using a refresh circuitry;
skipping, by the refresh controller, the refresh operation on the at least one memory row of the plurality of memory rows that is not selected; and
issuing, by the refresh controller, a refresh skip indication to the host upon completion of the refresh operation on the selected at least one memory row.

3. A memory device comprising:
at least one memory array including a plurality of memory cells, wherein the plurality of memory cells are arranged on each memory row of a plurality of memory rows;
a refresh-row selection circuitry including at least one row condition cell (RCC) connected to a memory row of the plurality of memory rows and at least one supplemental cell connected to the memory row of the plurality of memory rows; and
a refresh controller coupled to the refresh-row selection circuitry, the refresh controller configured to,
receive at least one refresh command from a host for the plurality of memory rows in the memory device,
enable the refresh-row selection circuitry for selecting at least one memory row of the plurality of memory rows by reading the at least one RCC and the at least one supplemental cell that are associated with the memory row of the plurality of memory rows, and
perform the refresh operation on the selected at least one memory row using a refresh circuitry.

4. The memory device of claim 3 , wherein the memory device includes a volatile semiconductor memory device.

5. The memory device of claim 3 , wherein the at least one RCC is at least one of a volatile memory cell or a non-volatile memory cell, and the at least one supplemental cell is a volatile memory cell.

6. The memory device of claim 3 , wherein the refresh-row selection circuitry comprises at least one of:
a digital verification module configured to perform a digital reading of the at least one RCC and the at least one supplemental cell; or
an analog verification module configured to perform an analog reading of the at least one RCC and the at least one supplemental cell connected to each memory row of the plurality of memory rows.

7. The memory device of claim 6 , wherein the digital verification module is further configured to:
read at least one data bit of the at least one RCC to classify each memory row into at least one condition, the at least one condition including at least one good condition and at least one bad condition, the at least one bad condition indicating the memory row has poor refresh performance compared with the at least one good condition;
read at least one data bit of the at least one supplemental cell to determine if the refresh operation is performed on each memory row in at least one previous refresh cycle; and
select the at least one memory row from the plurality of memory rows for the refresh operation if the at least one memory row is classified into at least one bad condition, and if the refresh operation is not performed on the at least one memory row in the at least one previous refresh cycle.

8. The memory device of claim 7 , wherein the host coupled to the memory device is configured to initialize the at least one data bit of the at least one RCC by:
accessing cell retention criteria maintained in the memory device during booting of the memory device, wherein the cell retention criteria includes information about at least one of (a) a cell retention profiling mechanism associated with an identification of bad memory cells in each memory row, a number of tests required to identify the bad memory cells, or (c) a retention time test to determine if each memory row is refreshed at a normal rate;
initiating a testing of the memory device using the cell retention criteria; and
initializing the at least one data bit of the at least one RCC depending on whether the at least one RCC satisfies the accessed cell retention criteria during the testing.

9. The memory device of claim 8 , wherein at least one of the host and the digital verification module are further configured to re-initialize the at least one data bit of the at least one RCC by at least one of:
detecting occurrence of at least one error correction code (ECC) error for the at least one RCC;
performing a scrub method at regular intervals; or
performing the scrub method when temperature of the memory device crosses a temperature threshold.

10. The memory device of claim 7 , wherein the digital verification module is further configured to initialize the at least one data bit of the at least one supplemental cell depending on whether the refresh operation is performed on corresponding each memory row in a current refresh cycle.

11. The memory device of claim 10 , wherein the digital verification module is further configured to refresh the at least one supplemental cell upon refreshing the at least one memory row connected to the corresponding at least one supplemental cell.

12. The memory device of claim 6 , wherein the analog verification module is further configured to:
read at least one comparison voltage stored in the at least one RCC connected to each memory row of the plurality of memory rows;
select at least one reference voltage from a plurality of reference voltages maintained by a voltage generation circuitry based on the read at least one stored comparison voltage of the at least one RCC;
read a voltage of the at least one supplemental cell connected to each memory row of the plurality of memory rows;
compare the read voltage of the at least one supplemental cell with the selected at least one reference voltage using a comparator; and
select the at least one memory row from the plurality of memory rows if the read voltage of the at least one supplemental cell is less than the selected at least one reference voltage.

13. The memory device of claim 12 , wherein the at least one RCC is configured to store the comparison voltage depending on whether the at least one RCC satisfies the cell retention criteria during the testing of the memory device.

14. The memory device of claim 12 , wherein the at least one RCC

Assignees

• Samsung Electronics Co Ltd

Inventors

• Atishay
• B K Anirudh
• Verma Rajeev
• Thummala Vishnu Charan

Classifications

• G11C11/40611

  External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh · CPC title

• G06F11/1072

  in multilevel memories · CPC title

• G06F11/1044

  with specific ECC/EDC distribution · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title