System and method for performing per-bank memory refresh

Patent metadata

Field	Value
Publication number	US-10777252-B2
Application number	US-201816109720-A
Country	US
Kind code	B2
Filing date	Aug 22, 2018
Priority date	Aug 22, 2018
Publication date	Sep 15, 2020
Grant date	Sep 15, 2020

Abstract

A method and apparatus for performing opportunistic refreshes of memory banks is disclosed. Refresh circuitry in a memory controller performs a refresh on each bank of a multi-bank memory at least once during a given refresh interval. At the beginning of an interval, memory banks for which there are no pending transactions (e.g., reads or writes) may be refreshed. During a first portion of the interval, refresh may be skipped for memory banks for which transactions are pending. In a second portion of the interval, refreshes are performed on memory banks that have not been refreshed during the interval, which may cause some memory transactions to be delayed.

First claim

What is claimed is:

1. An apparatus comprising:
a memory, wherein the memory is subdivided into a plurality of banks; and
a memory controller coupled to the memory, wherein the memory controller includes a refresh circuit configured to cause the plurality of banks to be refreshed within ones of a number of recurring intervals of time, and wherein the refresh circuit, when operating in a first mode, is further configured to:
cause, during a first sub-interval of a particular interval, a refresh to be performed for ones of the plurality of banks for which no transactions are pending, but not for ones of the plurality of banks for which transactions are pending; and
cause a refresh to be performed, during a second sub-interval of the particular interval that is subsequent to the first sub-interval, for ones of the plurality of banks that have not previously been refreshed during the particular interval.

2. The apparatus as recited in claim 1 , wherein the refresh circuit includes a timer configure to track an amount of time remaining in a current one of the recurring intervals, and further configured to determine when the first sub-interval has completed.

3. The apparatus as recited in claim 1 , wherein the refresh circuit is further configured to, during the second sub-interval, select an order in which ones of the plurality of banks are to be refreshed based on an amount of time required to refresh the ones of the plurality of banks.

4. The apparatus as recited in claim 1 , wherein responsive to determining that each of the plurality of banks has pending transactions at a beginning of a current interval, the refresh circuit is configured to cause banks having a fewest number of pending transactions to be refreshed first.

5. The apparatus as recited in claim 1 , wherein the refresh circuit includes a scoreboard configured to track which ones of the plurality of banks have been refreshed within a current interval.

6. The apparatus as recited in claim 1 , wherein the refresh circuit is further configured to, during the first sub-interval, cause a refresh to be performed on ones of the plurality of banks responsive to those ones of the plurality of banks completing transactions.

7. The apparatus as recited in claim 1 , wherein the refresh circuit includes an arbitration circuit configured to determine an order in which ones of the plurality of banks are to be refreshed.

8. The apparatus as recited in claim 1 , wherein the refresh circuit includes a refresh counter configured to track a number of pending refresh commands.

9. The apparatus as recited in claim 1 , wherein the refresh circuit is further configured to operate in a second mode, wherein during operation in the second mode, the refresh circuit is configured to delay transactions between the memory controller and the memory irrespective of an amount of time remaining in an interval during which operation in the second mode occurs.

10. A method comprising:
performing, during operation of a refresh circuit in a first mode, a refresh of a first subset of a plurality of memory banks during a first sub-interval of a refresh interval and responsive to determining that the first subset of the plurality of memory banks have no pending memory transactions;
skipping refresh for a second subset of the plurality of memory banks during the first sub-interval of the refresh interval and elapsing of a predetermined time thereafter based on determining that memory banks of the second subset have one or more pending transactions; and
causing, during a second sub-interval of the refresh interval, a refresh of remaining ones of the plurality of memory banks that have not been refreshed during the refresh interval.

11. The method as recited in claim 10 , further comprising refreshing particular ones of the memory banks within the first sub-interval responsive to determining that pending memory transactions involving the particular ones of the memory banks have been completed.

12. The method as recited in claim 10 , further comprising the refresh circuit maintaining a record of which ones of the plurality of banks has been refreshed during the refresh interval.

13. The method as recited in claim 10 , further comprising an arbitration circuit arbitrating an order in which banks of the plurality of banks are to be refreshed.

14. The method as recited in claim 10 , further comprising the refresh circuit operating in a second mode, wherein operating in the second mode includes the refresh circuit delaying transactions to particular ones of the memory banks while causing refreshes to be performed for each of the plurality of memory banks.

15. A system comprising:
a memory, wherein the memory is subdivided into a plurality of banks; and
a memory controller coupled to the memory, wherein the memory controller includes a refresh circuit configured to cause the plurality of banks to be refreshed within ones of a number of recurring intervals of time, and wherein the refresh circuit, when operating in a first mode, is further configured to:
during operation in a first sub-interval of a given interval, prioritize memory transactions over performing refreshes, wherein prioritizing memory transactions comprises performing refreshes for ones of the plurality of banks for which no transactions are pending and delaying refresh for ones of the plurality of banks for which transactions are pending; and
during operation during a second sub-interval of the given interval following the first sub-interval, cause a refresh to be performed for ones of the banks for which a refresh has not been performed during the given interval.

16. The system as recited in claim 15 , wherein the refresh circuit includes a timer configured to determine when the first sub-interval has ended and the second sub-interval has begun.

17. The system as recited in claim 15 , wherein the refresh circuit is configured to, during the second sub-interval, prioritize ones of the plurality of banks for performing a refresh based on an amount of time required to refresh the ones of the plurality of banks.

18. The system as recited in claim 15 , wherein the refresh circuit includes a scoreboard configured to track which ones of the plurality of banks have been refreshed during the given interval.

19. The system as recited in claim 15 , wherein the refresh circuit is configured to, during the first sub-interval, cause a refresh to be performed on ones of the plurality of banks responsive to those ones of the plurality of banks completing transactions.

20. The system as recited in claim 15 , wherein the refresh circuit is further configured to operate in a second mode, wherein during operation in the second mode, the refresh circuit is configured to delay transactions between the memory controller and the memory irrespective of an amount of time remaining in an interval during which operation in the second mode occurs.

Assignees

• Apple Inc

Inventors

• Fu Peter
• Mathews Gregory S
• Hsuing Kai Lun
• Keil Shane J

Classifications

• G11C11/40603 Primary

  Arbitration, priority and concurrent access to memory cells for read/write or refresh operations · CPC title

• G06F13/10

  Program control for peripheral devices (G06F13/14 - G06F13/42 take precedence) · CPC title

• G06F13/12

  using hardware independent of the central processor, e.g. channel or peripheral processor · CPC title

• G06F13/1636

  using refresh · CPC title

• G11C11/40618

  Refresh operations over multiple banks or interleaving · CPC title