Method and structure to contact tight pitch conductive layers with guided vias using alternating hardmasks and encapsulating etchstop liner scheme

Patent metadata

Field	Value
Publication number	US-10032643-B2
Application number	US-201415528736-A
Country	US
Kind code	B2
Filing date	Dec 22, 2014
Priority date	Dec 22, 2014
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

Interconnect structures having alternating dielectric caps and an etchstop liner for semiconductor devices and methods for manufacturing such devices are described. According to an embodiment, an interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. The interconnect structure may also include one or more first interconnect lines in the ILD. A first dielectric cap may be positioned above a top surface of each of the first interconnect lines. Additional embodiments include one or more second interconnect lines in the ILD that are arranged in an alternating pattern with the first interconnect lines. A second dielectric cap may be formed above a top surface of each of the second interconnect lines. Embodiments may also include an etchstop liner that is formed over top surfaces of the first dielectric caps.

First claim

What is claimed is:

1. An interconnect structure comprising:
an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD;
one or more first interconnect lines in the ILD, wherein a first dielectric cap is above a top surface of each of the first interconnect lines, and wherein a top surface of the first dielectric cap is substantially coplanar with a top surface of the first hardmask;
one or more second interconnect lines in the ILD arranged in an alternating pattern with the first interconnect lines, wherein a second dielectric cap is above a top surface of each of the second interconnect lines; and
an etchstop liner over top surfaces of the first dielectric caps.

2. The interconnect structure of claim 1 , wherein the etchstop liner separates the first dielectric caps from the first interconnect lines.

3. The interconnect structure of claim 1 , wherein the etchstop liner separates the second dielectric caps from the second interconnect lines, and wherein the etchstop liner is also formed along sidewalls of the second dielectric caps and over the top surface of the first hardmask layer.

4. The interconnect structure of claim 1 , wherein the etchstop liner is formed over a top surface of the second dielectric caps.

5. The interconnect structure of claim 1 , wherein the etchstop liner is a material that has an etch selectivity of 10:1 or greater with respect to the first dielectric caps, the second dielectric caps, and the first hardmask layer during an etchstop liner etching process.

6. The interconnect structure of claim 5 , wherein the etchstop liner etching process is a wet etching process.

7. The interconnect structure of claim 6 , wherein a dry etching process selectively etches at least one of the first dielectric caps or the second dielectric caps.

8. The interconnect structure of claim 1 , wherein the first dielectric caps are a different material than the second dielectric caps.

9. The interconnect structure of claim 8 , wherein the first dielectric caps have an etch selectivity of 10:1 or greater with respect to the second dielectric caps for a given etching process.

10. The interconnect structure of claim 1 , further comprising one or more first through vias formed through the ILD, wherein a first dielectric cap is formed above top surfaces of the one or more first through vias.

11. The interconnect structure of claim 1 , further comprising one or more second through vias formed through the ILD, wherein a second dielectric cap is formed above top surfaces of the one or more second through vias.

12. The interconnect structure of claim 1 , wherein the first and second caps are a SiO x C y N z material, a metal oxide material, or a metal nitride material.

13. The interconnect structure of claim 1 , wherein the etchstop liner is an aluminum-oxide or a hafnium-oxide material.

14. The interconnect structure of claim 1 , wherein the first interconnect lines are spaced less than 25 nm from the second interconnect lines.

15. A method of forming interconnects comprising:
forming one or more first trenches into an interlayer dielectric (ILD);
disposing a first metal into the one or more first trenches to form first interconnect lines;
forming an etchstop liner over top surfaces of the first interconnect lines;
forming first dielectric caps above the etchstop liner formed over the top surfaces of the first interconnect lines;
forming one or more second trenches into the ILD in an alternating pattern with the first trenches;
disposing a second metal into the one or more second trenches to form second interconnect lines;
forming an etchstop liner over top surfaces of the second interconnect lines and over top surfaces of the first dielectric caps; and
forming second dielectric caps above the second interconnect lines.

16. The method of claim 15 , wherein forming the first trenches comprises:
forming a backbone layer above a first hardmask layer formed over the ILD;
forming spacers on the backbone layer, wherein a portion of the first hardmask layer remains exposed between the spacers; and
etching through the exposed portions of the first hardmask layer and into the ILD underneath the exposed portions of the first hardmask layer.

17. The method of claim 16 , wherein forming the second trench comprises:
etching through the backbone layer; and
etching through portions of the first hardmask layer and into the ILD.

18. The method of claim 15 , further comprising:
etching through portions of the ILD formed underneath one or more of the first trenches prior to disposing the first metal into the first trenches; and
etching through portions of the ILD underneath one or more of the second trenches prior to disposing the second metal into the second trenches.

19. The method of claim 15 , wherein the etchstop liner has an etch selectivity of 10:1 or greater with respect to the first dielectric caps and the second dielectric caps.

20. The method of claim 15 , wherein the first interconnect lines are spaced apart from the second interconnect lines by less than 25 nm.

21. The method of claim 15 , wherein the first and second caps are a SiO x C y N z material, a metal oxide material, or a metal nitride material, and wherein the etchstop liner is an aluminum-oxide or a hafnium-oxide material.

22. A method of forming interconnects comprising:
forming a first hardmask layer above an interlayer dielectric (ILD);
forming a backbone hardmask above the first hardmask layer;
forming a spacer layer over the surfaces of the backbone hardmask and the exposed portions of the first hardmask layer;
etching through the spacer layer to form backbone spacers along the sidewalls of the backbone hardmask;
etching through the first hardmask layer and the ILD to form first trenches into the ILD;
disposing a first metal into the one or more first trenches to form first interconnect lines;
forming an etchstop liner over top surfaces of the first interconnect lines;
forming first dielectric caps above the etchstop liner formed over the top surfaces of the first interconnect lines;
etching through the backbone hardmask, and the portions of the first hardmask layer and the ILD below the backbone hardmask to form second trenches;
disposing a second metal into the one or more second trenches to form second interconnect lines;
forming an etchstop liner over top surfaces of the second interconnect lines and over top surfaces of the first dielectric caps;
forming second dielectric caps above the second interconnect lines; and
removing the backbone spacers.

23. The method of claim 22 , wherein the etchstop liner has an etch selectivity of 10:1 or greater with respect to the first dielectric caps and the second dielectric caps during an etchstop liner etching process.

24. The method of claim 23 , wherein the etchstop liner etching process is a wet etching process.

25. The method of claim 22 , wherein the first and second dielectric caps are a SiO x C y N z material, a metal oxide material, or a metal nitride material, and wherein the etchstop liner is an aluminum-oxide or a hafnium-oxide material.

Assignees

• Intel Corp

Inventors

• Chawla Jasmeet S
• Brain Ruth A
• Schenker Richard E
• Singh Kanwal Jit
• Myers Alan M

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W70/095

  of vias therein · CPC title

• H10W70/092

  Adapting interconnections, e.g. making engineering charges, repairing · CPC title