High performance refractory metal / copper interconnects to eliminate electromigration

US9536830B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9536830-B2
Application numberUS-201313890642-A
CountryUS
Kind codeB2
Filing dateMay 9, 2013
Priority dateMay 9, 2013
Publication dateJan 3, 2017
Grant dateJan 3, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An interconnect structure and method of making the same. A preferred interconnect structure has a first interconnect including a first dual damascene via and narrow line and a second interconnect at the same level as the first including a second dual damascene via and wider line. The first and second interconnects may have different aspect ratio and may have different line heights while being co-planar with each other. The second line of the second interconnect may abut or partially surround the first line of the first interconnect. The first interconnect includes a refractory metal material as the main conductor, whereas the second interconnect includes a lower resistivity material as its main conductor.

First claim

Opening claim text (preview).

We claim: 1. A method of forming a hybrid interconnect structure comprising: forming a first damascene line filled with a first conductor, the first damascene line having a first line width; and forming a second damascene line filled with a second conductor in the same interconnection level as the first damascene line, the second damascene line having a second line width; wherein the first line width is less than the second line width, and the first conductor is a refractory metal, the second conductor is a copper alloy, and wherein a vertical portion of a liner of the first damascene line abuts a vertical portion of a liner of the second damascene line. 2. The method of claim 1 , wherein the second conductor has a resistivity less than the first conductor. 3. The method of claim 1 , wherein the first damascene line and the second damascene line are in electrical contact with each other. 4. The method of claim 1 , wherein a first line opening of the first damascene line has a first line height and a second line opening of the second damascene line has a second line height wherein the first line height is greater than the second line height. 5. The method of claim 4 , wherein first line height is at least 1.5 times greater than the second line height. 6. The method of claim 1 , wherein an aspect ratio of the first damascene line is greater than an aspect ratio of the second damascene line. 7. A method of forming a hybrid structure comprising: forming a first dual damascene opening in a dielectric layer, the first dual damascene opening comprising a first line opening above a first via opening; forming a first liner along sidewalls and a bottom of the first dual damascene opening and on top of the dielectric layer; depositing a first conductor on top of the first liner within the first dual damascene opening and on top of the first liner above the dielectric layer; planarizing the first conductor and first liner such that upper surfaces of both the first conductor and the first liner are co-planar with an upper surface of the dielectric layer; forming a second dual damascene opening in the dielectric layer while protecting at least a portion of both the first conductor and the first liner, the second dual damascene opening comprising a second line opening above a second via opening, the second dual damascene opening intersects at least with a portion of the first liner such that a vertical portion of the first liner is exposed by forming the second dual damascene opening, and an aspect ratio of the first line opening is greater than an aspect ratio of the second line opening; forming a second liner above and covering the first conductor, and along sidewalls and a bottom of the second dual damascene opening and on top of the dielectric layer; depositing a second conductor on top of the second liner within the second dual damascene opening and on top of the second liner above the dielectric layer, wherein a vertical portion of the second liner is in contact with a vertical portion of the first liner such that a distance between the first conductor and the second conductor is substantially equal to a wall thickness of the first liner plus a wall thickness of the second liner; and planarizing the second conductor and second liner such that upper surfaces of both the second conductor and the second liner are co-planar with the upper surface of the dielectric layer. 8. The method of claim 7 , wherein the first conductor and the second conductor are in electrical contact with each other. 9. The method of claim 7 , wherein the first line opening has a first line height and the second line opening has a second line height wherein the first line height is greater than the second line height. 10. The method of claim 7 , wherein the first line opening has a first line width and the second line opening has a second line width wherein the first line width is less than the second line width. 11. The method of claim 7 , wherein the second conductor has a resistivity less than the first conductor. 12. The structure of claim 7 , wherein the first conductor comprises a refractory metal.

Assignees

Inventors

Classifications

  • Cross-sectional shapes or dispositions of interconnections · CPC title

  • Barrier, adhesion or liner layers · CPC title

  • H10W20/43Primary

    Layouts of interconnections · CPC title

  • H01L23/528Primary

    Electricity · mapped topic

  • Electricity · mapped topic

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Frequently asked questions

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What does patent US9536830B2 cover?
An interconnect structure and method of making the same. A preferred interconnect structure has a first interconnect including a first dual damascene via and narrow line and a second interconnect at the same level as the first including a second dual damascene via and wider line. The first and second interconnects may have different aspect ratio and may have different line heights while being c…
Who is the assignee on this patent?
IBM, Globalfoundries Inc
What technology area does this patent fall under?
Primary CPC classification H10W20/43. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 03 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).