Damascene wires with top via structures

Patent metadata

Field	Value
Publication number	US-9613861-B2
Application number	US-201514818419-A
Country	US
Kind code	B2
Filing date	Aug 5, 2015
Priority date	Aug 5, 2015
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

Damascene wires with top via structures and methods of manufacture are provided. The semiconductor structure includes a damascene wiring structure with an integrally formed top via structure in self-alignment with the damascene wiring structure which is underneath the integrally formed top via structure.

First claim

What is claimed:

1. A semiconductor structure comprising a damascene wiring structure with an integrally formed top via structure in self-alignment with the damascene wiring structure which is underneath the integrally formed top via structure,
wherein the damascene wiring structure has cut ends.

2. The semiconductor structure of claim 1 , further comprising a liner on vertical sidewalls of the damascene wiring structure and the integrally formed top via structure.

3. The semiconductor structure of claim 2 , wherein the liner is further provided on a top surface of the damascene wiring structure and sloped sidewalls of the integrally formed top via structure.

4. The semiconductor structure of claim 3 , wherein the sloped sidewalls form a lower portion having a wider width than an upper portion.

5. The semiconductor structure of claim 4 , wherein the liner on the vertical sidewalls of the damascene structure comprises silicon nitride.

6. The semiconductor structure of claim 5 , wherein the sloped sidewalls are downward sloping such that the lower portion of the integrally formed top via structure has the wider width than the upper portion of the integrally formed top via structure.

7. The semiconductor structure of claim 1 , further comprising a wiring structure in direct electrical contact with an upper portion of the integrally formed top via structure.

8. The semiconductor structure of claim 7 , wherein the wiring structure includes a liner formed on its sidewalls and on a top surface of the integrally formed top via structure.

9. The semiconductor structure of claim 1 , wherein the cut ends of the damascene wiring structure are covered with a liner.

10. The semiconductor structure of claim 1 , wherein the damascene wiring structure is a copper damascene wire.

11. The semiconductor structure of claim 1 , wherein the integrally formed top via structure and the damascene wiring structure are of a same material.

12. A structure comprising:
a damascene wiring structure formed in a dielectric layer;
a top etched via structure in self-alignment with the damascene wiring structure; and
a liner on vertical sidewalls of the damascene wiring structure and the top etched via structure,
wherein the liner is provided on a top surface of the damascene wiring structure and sloped sidewalls of the top etched via structure, and
the damascene wiring structure has cut ends which are covered with the liner.

13. The semiconductor structure of claim 12 , wherein:
the sloped sidewalls form a lower portion in contact with the damascene wiring structure having a wider width than an upper portion.

14. The semiconductor structure of claim 13 , further comprising a wiring structure in direct electrical contact with an upper portion of the etched via structure and a liner on sidewalls of the wiring structure and on a top surface of the etched via structure.

15. The semiconductor structure of claim 12 , wherein the damascene wiring structure is a copper damascene wire.

16. The semiconductor structure of claim 15 , wherein the top etched via structure and the damascene wiring structure are of a same material.

17. The semiconductor structure of claim 12 , further comprising another liner on a bottom surface of the top etched via structure,
wherein the another liner comprises tungsten cobalt and has a thickness of about 5-10 nm, and the sloped sidewalls are downward sloping.

Assignees

• Globalfoundries Inc

Inventors

• Anderson Brent A
• Nowak Edward J

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/063

  by forming conductive members before forming protective insulating material · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title