Amplifier circuitry for carrier aggregation

Patent metadata

Field	Value
Publication number	US-11595075-B2
Application number	US-202117341159-A
Country	US
Kind code	B2
Filing date	Jun 7, 2021
Priority date	Sep 22, 2020
Publication date	Feb 28, 2023
Grant date	Feb 28, 2023

Abstract

An electronic device may include wireless circuitry with a baseband processor, a transceiver circuit, a front-end module, and an antenna. The front-end module may include amplifier circuitry such as a low noise amplifier for amplifying received radio-frequency signals. The amplifier circuitry is operable in a non-carrier-aggregation mode and a carrier aggregation mode. The amplifier circuitry may include an input transformer that is coupled to multiple amplifier stages such as a common gate amplifier stage, a cascode amplifier stage, and a common source amplifier stage. The common gate amplifier stage may include switches for selectively activating a set of cross-coupled capacitors to help maintain input impedance matching in the non-carrier-aggregation mode and the carrier-aggregation mode. The common source amplifier stage may include additional switches for activating and deactivating the common source amplifier stage to help maintain the gain in the non-carrier-aggregation mode and the carrier-aggregation mode.

First claim

What is claimed is:

1. Amplifier circuitry comprising:
an input port configured to receive radio-frequency signals from an antenna;
transformer circuitry coupled to the input port;
a first amplifier coupled to the transformer circuitry; and
a second amplifier coupled to the transformer circuitry, the first amplifier and the second amplifier each including
a first amplifier stage having an input coupled to the transformer circuitry and having an output,
a second amplifier stage coupled to the output of the first amplifier stage, the second amplifier stage coupled to a bias voltage configured to activate and deactivate the second amplifier stage, and
an output port coupled to the output of the first amplifier stage.

2. The amplifier circuitry of claim 1 , wherein the first amplifier stage comprises a common gate amplifier stage.

3. The amplifier circuitry of claim 2 , wherein the second amplifier stage comprises a common source amplifier stage.

4. The amplifier circuitry of claim 1 , wherein the second amplifier stage comprises a common source amplifier stage.

5. The amplifier circuitry of claim 1 , wherein the bias voltage is configured to activate and deactivate the second amplifier stage in a carrier-aggregation mode and a non-carrier-aggregation mode.

6. The amplifier circuitry of claim 1 , wherein the transformer circuitry comprises:
a primary coil having a first terminal coupled to the input port and a second terminal coupled to a ground line;
a first adjustable capacitor coupled in series between the input port and the first terminal; and
a second adjustable capacitor having a first terminal coupled to the input port and a second terminal coupled to the ground line.

7. The amplifier circuitry of claim 6 , wherein the transformer circuitry comprises:
a first secondary coil coupled to the input of the first amplifier stage in the first amplifier;
a third adjustable capacitor coupled in parallel with the first secondary coil, the third adjustable capacitor being configured to control an input impedance of the first amplifier;
a second secondary coil coupled to the input of the first amplifier stage in the second amplifier; and
a fourth adjustable capacitor coupled in parallel with the second secondary coil, the fourth adjustable capacitor being configured to control an input impedance of the second amplifier.

8. The amplifier circuitry of claim 1 , wherein the first amplifier stage in each of the first amplifier and the second amplifier comprises:
a first transistor having a source terminal coupled to the input of the first amplifier stage, a drain terminal coupled to the output of the first amplifier stage, and a gate terminal;
a second transistor having a source terminal coupled to the input of the first amplifier stage, a drain terminal coupled to the output of the first amplifier stage, and a gate terminal;
a first capacitor having a first terminal coupled to the gate terminal of the first transistor and having a second terminal coupled to the source terminal of the second transistor; and
a second capacitor having a first terminal coupled to the gate terminal of the second transistor and having a second terminal coupled to the source terminal of the first transistor.

9. The amplifier circuitry of claim 1 , wherein each of the first amplifier and the second amplifier comprises a cascode amplifier stage having:
an input coupled to the output of the first amplifier stage;
an output coupled to the output port;
a first transistor having a source terminal coupled to the input of the cascode amplifier stage, a drain terminal coupled to the output of the cascode amplifier stage, and a gate terminal coupled to a cascode bias line; and
a second transistor having a source terminal coupled to the input of the cascode amplifier stage, a drain terminal coupled to the output of the cascode amplifier stage, and a gate terminal coupled to the cascode bias line.

10. The amplifier circuitry of claim 1 , wherein the second amplifier stage in each of the first amplifier and the second amplifier comprises:
a first transistor having a source terminal coupled to a ground line, a gate terminal coupled to the output of the first amplifier stage, and a drain terminal coupled to the output port; and
a second transistor having a source terminal coupled to the ground line, a gate terminal coupled to the output of the first amplifier stage, and a drain terminal coupled to the output port.

11. The amplifier circuitry of claim 1 , wherein the first amplifier and the second amplifier each comprises:
an output coil having a first terminal coupled to the output port, a second terminal coupled to the output port, and a center tap coupled to a positive power supply line.

12. The amplifier circuitry of claim 11 , wherein the first amplifier and the second amplifier each comprises:
an adjustable output capacitor having a first terminal coupled to the first terminal of the output coil and a second terminal coupled to the second terminal of the output coil.

13. A method of operating amplifier circuitry, comprising:
with an input port, receiving radio-frequency signals from an antenna;
with transformer circuitry, coupling the radio-frequency signals from the input port to a first amplifier;
with the transformer circuitry, coupling the radio-frequency signals from the input port to a second amplifier;
with a first amplifier stage in each of the first and second amplifiers, receiving the radio-frequency signals from the transformer circuitry and outputting corresponding amplified signals;
with a second amplifier stage in each of the first and second amplifiers, receiving the amplified signals and outputting corresponding output signals; and
adjusting a bias voltage in the second amplifier stage in each of the first and second amplifiers.

14. The method of claim 13 , wherein the first amplifier stage comprises a common gate amplifier stage.

15. The method of claim 14 , wherein the second amplifier stage comprises a common source amplifier stage.

16. The method of claim 13 , wherein the second amplifier stage comprises a common source amplifier stage.

17. The method of claim 13 , wherein adjusting the bias voltage comprises adjusting the bias voltage in the second amplifier stage in each of the first and second amplifiers in a carrier-aggregation mode and a non-carrier-aggregation mode.

18. An electronic device operable in a first mode and a second mode, comprising:
an antenna configured to receive radio-frequency signals;
a transceiver configured to generate baseband signals based on the radio-frequency signals;
a baseband processor configured to receive the baseband signals; and
amplifier circuitry configured to receive the radio-frequency signals from the antenna and to output corresponding amplified signals to the transceiver, the amplifier circuitry having
an input port,
transformer circuitry coupled to the input port,
a first amplifier stage having an input coupled to the transformer circuitry and having an output,
a second amplifier stage coupled to the output of the first amplifier stage, the second amplifier stage coupled to a bias voltage configured to control the second amplifier stage in the first mode and the second mode, and
an output port coupled to the output of the first amplifier stage.

19. The electronic device of claim 18 , wherein the first amplifier stage comprises a common gate amplifier stage and wherein the second amplifier stage comprises a common source amplifier stage.

Assignees

• Apple Inc

Inventors

• Mohammadnezhad Seyed Mohammad Hossein
• Yao Xi
• Ismail Aly

Classifications

• H03F3/265

  with field-effect transistors only · CPC title

• H03F2203/7209

  the gated amplifier being switched from a first band to a second band · CPC title

• H03F3/68

  Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics {(power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602)} · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H03F1/223

  with MOSFET's · CPC title