Low-noise amplifier (LNA) with capacitive attenuator

Patent metadata

Field	Value
Publication number	US-10033340-B1
Application number	US-201715400078-A
Country	US
Kind code	B1
Filing date	Jan 6, 2017
Priority date	Jan 6, 2017
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

Certain aspects of the present disclosure generally relate to a multi-output amplifier implemented using a capacitive attenuator. For example, the multi-output amplifier generally includes a first capacitive attenuator coupled to an input node of the multi-output amplifier. In certain aspects, the multi-output amplifier also includes a first amplification stage having an input coupled to a tap node of the first capacitive attenuator and an output coupled to a first output node of the multi-output amplifier, and a second amplification stage having an output coupled to a second output node of the multi-output amplifier. For certain aspects, the multi-output amplifier includes a second capacitive attenuator coupled to the input node of the multi-output amplifier, and the second amplification stage may have an input coupled to a tap node of the second capacitive attenuator.

First claim

What is claimed is:

1. A multi-output amplifier comprising:
a first capacitive attenuator coupled to an input node of the multi-output amplifier;
a first amplification stage having an input coupled to a tap node of the first capacitive attenuator and an output coupled to a first output node of the multi-output amplifier, wherein the first amplification stage comprises a first transistor having a drain coupled to a source of a second transistor, the second transistor being coupled to the first output node, and wherein a gate of the first transistor is coupled to the tap node of the first capacitive attenuator; and
a second amplification stage having an output coupled to a second output node of the multi-output amplifier, wherein the second amplification stage comprises a third transistor having a drain coupled to a source of a fourth transistor, the fourth transistor being coupled to the second output node.

2. The multi-output amplifier of claim 1 , wherein the second amplification stage has an input coupled to the tap node of the first capacitive attenuator.

3. The multi-output amplifier of claim 1 , further comprising:
a second capacitive attenuator coupled to the input node of the multi-output amplifier, wherein the second amplification stage has an input coupled to a tap node of the second capacitive attenuator.

4. The multi-output amplifier of claim 3 , wherein:
the third transistor is coupled to the tap node of the second capacitive attenuator.

5. The multi-output amplifier of claim 1 , wherein the first capacitive attenuator comprises:
a first capacitor having a first terminal coupled to the input node; and
at least one second capacitor coupled between a second terminal of the first capacitor and a reference potential of the multi-output amplifier.

6. The multi-output amplifier of claim 5 , wherein a gain of the first amplification stage is configured to be adjusted based on a capacitance of the at least one second capacitor.

7. The multi-output amplifier of claim 5 , wherein a capacitance of at least one of the first capacitor or the second capacitor is variable.

8. The multi-output amplifier of claim 5 , wherein a gain of the multi-output amplifier is configured to be adjusted based on a capacitance of the at least one second capacitor.

9. The multi-output amplifier of claim 1 , further comprising:
a resistive device coupled between the input node and a reference potential of the multi-output amplifier.

10. The multi-output amplifier of claim 9 , wherein a gain of the multi-output amplifier and an input impedance of the multi-output amplifier are adjusted based on a resistance of the resistive device.

11. The multi-output amplifier of claim 1 , further comprising:
a second capacitive attenuator coupled to the input node, wherein a gate of the third transistor is coupled to a tap node of the second capacitive attenuator.

12. The multi-output amplifier of claim 11 , wherein the gates of the first transistor and the third transistor are shorted together.

13. The multi-output amplifier of claim 1 , further comprising:
a high-gain amplifier having an input coupled to the input node of the multi-output amplifier and a first output coupled to the first output node and a second output coupled to the second output node, wherein the high-gain amplifier has a higher gain than the first amplification stage and the second amplification stage.

14. The multi-output amplifier of claim 13 , further comprising:
a resistive device selectively coupled between the input node and a reference potential of the multi-output amplifier, wherein the multi-output amplifier is capable of disabling the resistive device such that the first amplification stage and the second amplification stage have a high input impedance.

15. The multi-output amplifier of claim 14 , wherein the multi-output amplifier is capable of disabling the high-gain amplifier.

16. The multi-output amplifier of claim 15 , wherein the resistive device is configured to be disabled when the high-gain amplifier is enabled.

17. A multi-output amplifier comprising:
a first capacitive attenuator coupled to an input node of the multi-output amplifier;
a first amplification stage having an input coupled to a tap node of the first capacitive attenuator and an output coupled to a first output node of the multi-output amplifier;
a second amplification stage having an output coupled to a second output node of the multi-output amplifier; and
a switch network, wherein the first capacitive attenuator is coupled to the input node through the switch network.

18. The multi-output amplifier of claim 17 , wherein the switch network is configured to selectively disable the first amplification stage and the second amplification stage.

19. A method for signal amplification, comprising:
attenuating an input signal via a first capacitive attenuator;
generating a first amplified output signal based on the attenuated input signal via a first amplification stage of a multi-output amplifier, wherein the first amplification stage comprises a first transistor having a drain coupled to a source of a second transistor, the second transistor being coupled to a node for providing the first amplified output signal, and wherein a gate of the first transistor is coupled to a tap node of the first capacitive attenuator; and
generating a second amplified output signal based on the input signal via a second amplification stage of the multi-output amplifier, wherein the second amplification stage comprises a third transistor having a drain coupled to a source of a fourth transistor, the fourth transistor being coupled to a node for providing the second amplified output signal.

20. The method of claim 19 , wherein the second amplified output signal is generated based on the attenuated input signal.

21. The method of claim 19 , further comprising:
attenuating the input signal via a second capacitive attenuator, wherein generating the second amplified output signal is based on the attenuated input signal from the second capacitive attenuator.

22. The method of claim 19 , further comprising:
setting a gain for the generation of the first amplified output signal by adjusting a capacitance of the first capacitive attenuator.

23. The method of claim 19 , further comprising:
setting a gain for the generation of the first amplified output signal and the second amplified output signal by adjusting a resistance of a resistive device coupled to an input node of the multi-output amplifier.

24. The method of claim 19 , further comprising:
setting an input impedance of the multi-output amplifier by adjusting a resistance of a resistive device coupled to an input node of the multi-output amplifier.

25. The method of claim 19 , further comprising:
decoupling a resistive device from an input node of the multi-output amplifier such that the first amplification stage and the second amplification stage have a high input impedance.

26. The method of claim 19 , further comprising:
selectively disabling at least one of the generation of the first amplified output signal or the generation of the second amplified output signal.

27. An apparatus for signal amplification, comprising:
first means for capacitively attenuating an input signal;
means for generating a first amplified output signal based on the attenuated input signal, wherein the means for generat

Assignees

• Qualcomm Inc

Inventors

• Hanafi Bassel
• Abdelhalem Sherif
• Lakdawala Hasnain

Classifications

• H03G1/0017

  the device being at least one of the amplifying solid-state elements · CPC title

• H03F1/223

  with MOSFET's · CPC title

• H03F2200/231

  the input of an amplifier can be switched on or off by a switch to amplify or not an input signal · CPC title

• H03F2200/111

  the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not · CPC title

• H03F3/21

  with semiconductor devices only {(H03F3/245 takes precedence)} · CPC title