Gain control in complementary common gate and common source amplifiers

Patent metadata

Field	Value
Publication number	US-9407226-B2
Application number	US-201414575851-A
Country	US
Kind code	B2
Filing date	Dec 18, 2014
Priority date	Dec 18, 2014
Publication date	Aug 2, 2016
Grant date	Aug 2, 2016

Abstract

Gain control in complementary common gate and common source amplifiers is disclosed. In an exemplary embodiment, an apparatus includes a first amplifier stage configured to amplify an input signal at an input terminal to generate a first amplified signal. The first amplifier stage includes a current diverter that selectively diverts current to set a gain of the first amplifier stage. The apparatus also includes a second amplifier stage configured to amplify the input signal at the input terminal to generate a second amplified signal. The second amplifier stage includes a gain control circuit to set a gain of the second amplifier stage.

First claim

What is claimed is:

1. An apparatus comprising:
a first amplifier stage configured to amplify an input signal at an input terminal to generate a first amplified signal, the first amplifier stage having a current diverter configured to selectively divert a first current to set a gain of the first amplifier stage,
wherein the first amplifier stage is configured as a complementary common gate (CCG) amplifier that generates the first amplified signal as non-inverted with respect to the input signal and the second amplifier stage is configured as a complementary common source (CCS) amplifier that generates the second amplified signal as inverted with respect to the input signal; and
a second amplifier stage configured to amplify the input signal at the input terminal to generate a second amplified signal, the second amplifier stage having a gain control circuit to set a gain of the second amplifier stage.

2. The apparatus of claim 1 , the gain control circuit comprising parallel branches of complimentary cascode transistors that are selectively enabled to set the gain of the second amplifier stage.

3. The apparatus of claim 2 , further comprising a controller configured to output control signals to control the current diverter to set the gain of the first amplifier stage and to control the gain control circuit to set the gain of the second amplifier stage.

4. The apparatus of claim 3 , the controller configured to output first control signals to control the current diverter to divert a selected amount of the first current to a node that forms an AC ground to set the gain of the first amplifier stage to a selected gain setting, and the controller configured to output second control signals to selectively enabled the parallel branches of the complimentary cascode transistors to set the gain of the second amplifier stage to the selected gain setting.

5. The apparatus of claim 1 , the gain control circuit comprising a second current diverter configured to divert a selected amount of a second current to set the gain of the second amplifier stage.

6. An apparatus comprising:
a first amplifier stage configured to amplify an input signal at an input terminal to generate a first amplified signal, the first amplifier stage having a current diverter configured to selectively divert a first current to set a gain of the first amplifier stage;
a second amplifier stage configured to amplify the input signal at the input terminal to generate a second amplified signal, the second amplifier stage having a gain control circuit to set a gain of the second amplifier stage,
the gain control circuit comprising a second current diverter configured to divert a selected amount of a second current to set the gain of the second amplifier stage,
the current diverter configured to divert a selected amount of the first current to a node and the second current diverter configured to divert the selected amount of the second current to the node, the node forms an AC signal ground.

7. The apparatus of claim 6 , further comprising a capacitor coupled between the node and a signal ground, the selected amounts of the first and second currents flowing in opposite directions at the node resulting in a third current flowing between the node and the capacitor that is less than the first or second currents.

8. The apparatus of claim 6 , further comprising a controller configured to output control signals to control the current diverter to set the gain of the first amplifier stage and to control the second current diverter to set the gain of the second amplifier stage.

9. The apparatus of claim 1 , further comprising a summation circuit configured to receive the first and second amplified signals and to output a differential signal.

10. The apparatus of claim 9 , the summation circuit comprising a bias signal generator that generates a bias signal that biases the first and second amplifier stages.

11. The apparatus of claim 10 , the summation circuit comprising a transformer that receives the first and second amplified signals across a first winding, the first winding having a center tap that outputs a common mode voltage signal to the bias signal generator.

12. An apparatus comprising:
means for amplifying an input signal at an input terminal to generate a first amplified signal at a first output terminal, the first amplified signal non-inverted with respect to the input signal;
means for diverting a first current generated in response to the input signal to set a gain of the means for amplifying;
means for amplifying with signal inversion configured to amplify the signal at the input terminal to generate a second amplified signal at a second output terminal, the second amplified signal inverted with respect to the input signal; and
means for setting a gain of the means for amplifying with signal inversion, the means for setting the gain comprising parallel branches of complimentary cascode transistors that are selectively enabled to set the gain of the means for amplifying with signal inversion.

13. The apparatus of claim 12 , the means for amplifying comprising a complementary common gate (CCG) amplifier that generates the first amplified signal.

14. The apparatus of claim 12 , the means for amplifying with signal inversion comprising a complementary common source (CCS) amplifier that generates the second amplified signal.

15. The apparatus of claim 12 , the means for diverting the first current configured to steer a selected portion of the first current to a node that forms an AC signal ground.

16. The apparatus of claim 15 , further comprising a capacitor coupled between the node and a signal ground.

17. The apparatus of claim 12 , the means for setting the gain comprising means for diverting a second current to set the gain of the means for amplifying with signal inversion.

18. The apparatus of claim 12 , further comprising means for controlling that outputs control signals to control the means for diverting the first current and the means for setting the gain.

Assignees

• Qualcomm Inc

Inventors

• Liao Chih-Fan

Classifications

• H03G3/3036 Primary

  in high-frequency amplifiers or in frequency-changers (H03G3/3052, H03G3/32, H03G3/34 take precedence) · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H03F2200/54

  Two or more capacitor coupled amplifier stages in cascade · CPC title

• H03F3/19

  with semiconductor devices only · CPC title

• H03F1/0272 Primary

  by using a signal derived from the output signal · CPC title