Three-dimensional memory devices

Patent metadata

Field	Value
Publication number	US-11574922-B2
Application number	US-202016913611-A
Country	US
Kind code	B2
Filing date	Jun 26, 2020
Priority date	May 27, 2020
Publication date	Feb 7, 2023
Grant date	Feb 7, 2023

Abstract

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, an N-type doped semiconductor layer above the memory stack, a plurality of channel structures each extending vertically through the memory stack into the N-type doped semiconductor layer, and a source contact above the memory stack and in contact with the N-type doped semiconductor layer. An upper end of each of the plurality of channel structures is flush with or below a top surface of the N-type doped semiconductor layer.

First claim

What is claimed is:

1. A three-dimensional (3D) memory device, comprising:
a substrate;
a peripheral circuit on the substrate;
a memory stack comprising interleaved conductive layers and dielectric layers above the peripheral circuit;
an N-type doped semiconductor layer above the memory stack;
a plurality of channel structures each extending vertically through the memory stack into the N-type doped semiconductor layer, wherein an upper end of each of the plurality of channel structures is surrounded by a semiconductor material and is flush with or below a top surface of the N-type doped semiconductor layer; and
a source contact above the memory stack, the source contact being electrically connected with one of the plurality of channel structures through the semiconductor material that comprises a first doping concentration different from a second doping concentration of the N-type doped semiconductor layer.

2. The 3D memory device of claim 1 , wherein the N-type doped semiconductor layer comprises polysilicon.

3. The 3D memory device of claim 1 , wherein the N-type doped semiconductor layer comprises single crystalline silicon.

4. The 3D memory device of claim 1 , wherein each of the channel structures comprises a memory film and a semiconductor channel, and an upper end of the memory film is below an upper end of the semiconductor channel.

5. The 3D memory device of claim 4 , wherein the upper end of the memory film is below the top surface of the N-type doped semiconductor layer, and the upper end of the semiconductor channel is flush with or below the top surface of the N-type doped semiconductor layer.

6. The 3D memory device of claim 4 , wherein a portion of the semiconductor channel extending into the N-type doped semiconductor layer comprises doped polysilicon.

7. The 3D memory device of claim 6 , further comprising a semiconductor plug, the semiconductor plug comprising the semiconductor material that surrounds and is in contact with the portion of the semiconductor channel.

8. The 3D memory device of claim 1 , further comprising an interconnect layer above and electrically connected to the source contact.

9. The 3D memory device of claim 8 , further comprising a first contact through the N-type doped semiconductor layer, wherein the N-type doped semiconductor layer is electrically connected to the peripheral circuit through at least the source contact, the interconnect layer, and the first contact.

10. The 3D memory device of claim 8 , further comprising a second contact through the N-type doped semiconductor layer, wherein the interconnect layer comprises a contact pad electrically connected to the second contact.

11. The 3D memory device of claim 1 , further comprising an insulating structure extending vertically through the memory stack and extending laterally to separate the plurality of channel structures into a plurality of blocks.

12. The 3D memory device of claim 11 , wherein the insulating structure is filled with one or more dielectric materials.

13. The 3D memory device of claim 11 , wherein a top surface of the insulating structure is flush with a bottom surface of the N-type doped semiconductor layer.

14. The 3D memory device of claim 1 , further comprising a bonding interface between the peripheral circuit and the memory stack.

15. A three-dimensional (3D) memory device, comprising:
a substrate;
a memory stack comprising interleaved conductive layers and dielectric layers above the substrate;
an N-type doped semiconductor layer above the memory stack; and
a plurality of channel structures each extending vertically through the memory stack into the N-type doped semiconductor layer,
wherein each of the plurality of channel structures comprises a memory film and a semiconductor channel, an upper end of the memory film being below an upper end of the semiconductor channel; and
the N-type doped semiconductor layer comprises a semiconductor plug surrounding and in contact with a portion of the semiconductor channel, and a doping concentration of the semiconductor plugs being different from a doping concentration of the rest of the N-type doped semiconductor layer.

16. The 3D memory device of claim 15 , further comprising an insulating structure extending vertically through the memory stack and extending laterally to separate the plurality of channel structures into a plurality of blocks.

17. The 3D memory device of claim 15 , further comprising a source contact above the memory stack and in contact with the N-type doped semiconductor layer.

18. A three-dimensional (3D) memory device, comprising:
a first semiconductor structure comprising a peripheral circuit;
a second semiconductor structure comprising:
a memory stack comprising interleaved conductive layers and dielectric layers;
an N-type doped semiconductor layer; and
a plurality of channel structures each extending vertically through the memory stack into the N-type doped semiconductor layer and electrically connected to the peripheral circuit, wherein the N-type doped semiconductor layer comprises a semiconductor plug surrounding a portion of each of the plurality of channel structures extending into the N-type doped semiconductor layer, and a doping concentration of the semiconductor plugs is different from a doping concentration of the rest of the N-type doped semiconductor layer; and

a bonding interface between the first semiconductor structure and the second semiconductor structure.

19. The 3D memory device of claim 18 , wherein the second semiconductor structure further comprises an insulating structure extending vertically through the memory stack and extending laterally to separate the plurality of channel structures into a plurality of blocks.

20. The 3D memory device of claim 18 , wherein the second semiconductor structure further comprises a source contact in contact with the N-type doped semiconductor layer.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Zhang Kun
• Zhou Wenxi
• Xia Zhiliang
• Huo Zongliang

Classifications

• H10B80/00

  Assemblies of multiple devices comprising at least one memory device covered by this subclass · CPC title

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title