Three-dimensional memory devices and methods for forming the same

Patent metadata

Field	Value
Publication number	US-2019081069-A1
Application number	US-201816047251-A
Country	US
Kind code	A1
Filing date	Jul 27, 2018
Priority date	Aug 21, 2017
Publication date	Mar 14, 2019
Grant date	—

Abstract

Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a NAND memory device includes a substrate, one or more peripheral devices on the substrate, a plurality of NAND strings above the peripheral devices, a single crystalline silicon layer above and in contact with the NAND strings, and interconnect layers formed between the peripheral devices and the NAND strings. In some embodiments, the NAND memory device includes a bonding interface at which an array interconnect layer contacts a peripheral interconnect layer.

First claim

What is claimed is:

1 . A NAND memory device, comprising:
a substrate; one or more peripheral devices on the substrate; a plurality of NAND strings above the one or more peripheral devices; a single crystalline silicon layer above and in contact with the plurality of NAND strings; and one or more first interconnect layers formed between the one or more peripheral devices and the plurality of NAND strings.

2 . The NAND memory device of claim 1 , further comprising an alternating conductor/dielectric stack, wherein each of the NAND strings comprises:
a semiconductor channel extending vertically through the alternating conductor/dielectric stack; a tunneling layer between the alternating conductor/dielectric stack and the semiconductor channel; and a storage layer between the tunneling layer and the alternating conductor/dielectric stack.

3 . The NAND memory device of claim 2 , further comprising a plurality of first contacts, wherein each of the plurality of first contacts extends vertically and comprises an upper end in contact with a conductor layer of the alternating conductor/dielectric stack.

4 . The NAND memory device of claim 2 , further comprising a second contact, wherein the second contact extends vertically through the alternating conductor/dielectric stack and comprises an upper end in contact with the single crystalline silicon layer.

5 . The NAND memory device of claim 1 , further comprising a second interconnect layer above the plurality of NAND strings, wherein the second interconnect layer comprises one or more conductor layers in one or more dielectric layers.

6 . The NAND memory device of claim 1 , wherein the plurality of NAND strings comprise a NAND string above another NAND string.

7 . The NAND memory device of claim 6 , wherein the NAND string and the another NAND string are electrically connected by a conductor.

8 . A NAND memory device, comprising:
a substrate; an alternating conductor/dielectric stack on the substrate; a plurality of NAND strings, wherein each of the plurality of NAND strings comprises:
a semiconductor channel extending vertically through the alternating conductor/dielectric stack;
a tunneling layer between the alternating conductor/dielectric stack and the semiconductor channel; and
a storage layer between the tunneling layer and the alternating conductor/dielectric stack; and
a single crystalline silicon layer above the plurality of NAND strings and in contact with the plurality of NAND strings.

9 . The NAND memory device of claim 8 , wherein each of the plurality of NAND strings further comprises an epitaxial plug at an upper end of the NAND string.

10 . The NAND memory device of claim 8 , further comprising a plurality of first contacts, wherein each of the plurality of first contacts is below and in contact with a lower end of a corresponding one of the plurality of NAND strings.

11 . The NAND memory device of claim 8 , further comprising a second contact, wherein the second contact extends vertically through the alternating conductor/dielectric stack and comprises an upper end in contact with the single crystalline silicon layer.

12 . The NAND memory device of claim 8 , wherein each of the plurality of NAND strings further comprises a select gate at an end of the NAND string.

13 . The NAND memory device of claim 8 , further comprising a peripheral device on the substrate and below the plurality of NAND strings.

14 . The NAND memory device of claim 8 , further comprising a first interconnect layer below the plurality of NAND strings, wherein the first interconnect layer comprises one or more conductor layers in one or more dielectric layers.

15 . The NAND memory device of claim 8 , further comprising a second interconnect layer above the plurality of NAND strings, wherein the second interconnect layer comprises one or more conductor layers in one or more dielectric layers.

16 . A method for forming a NAND memory device, comprising:
forming one or more peripheral devices on a first substrate; forming a plurality of NAND strings on a second substrate; positioning the plurality of NAND strings above the one or more peripheral devices, wherein the second substrate is above the plurality of NAND strings; joining the plurality of NAND strings and the one or more peripheral devices; and thinning the second substrate, so that the thinned second substrate serves as a single crystalline silicon layer above the plurality of NAND strings.

17 . The method of claim 16 , further comprising, prior to the joining of the plurality of NAND strings and the one or more peripheral devices, forming a first interconnect layer for the one or more peripheral devices.

18 . The method of claim 16 , further comprising, prior to the joining of the NAND strings and the one or more peripheral devices, forming a second interconnect layer for the plurality of NAND strings.

19 . The method of claim 16 , further comprising forming a third interconnect layer above the single crystalline silicon layer.

20 . The method of claim 16 , wherein the joining comprises joining via a thermal treatment and/or a plasma treatment.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Lu Zhenyu
• Chen Jun
• Zhu Jifeng
• Hu Yushi
• Tao Qian
• Yang Simon Shi-Ning
• Yang Steve Weiyi

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W72/07236

  Soldering or alloying · CPC title