Address fault detection in a flash memory system

Patent metadata

Field	Value
Publication number	US-10692548-B2
Application number	US-201916551593-A
Country	US
Kind code	B2
Filing date	Aug 26, 2019
Priority date	Mar 23, 2017
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

A system and method are disclosed for performing address fault detection in a flash memory system. In one embodiment, a flash memory system comprises a memory array comprising flash memory cells arranged in rows and columns, a row decoder for receiving a row address as an input, the row decoder coupled to a plurality of word lines, wherein each word line is coupled to a row of flash memory cells in the memory array, an address fault detection array comprising a column of memory cells, wherein each of the plurality of word lines is coupled to a memory cell in the column, and an analog comparator for comparing a current drawn by the column with a reference current and for indicating a fault if the current drawn by the column exceeds the reference current.

First claim

What is claimed is:

1. A flash memory system, comprising:
a memory array comprising flash memory cells arranged in rows and columns;
a row decoder for receiving a row address as an input, the row decoder coupled to a plurality of word lines, wherein each word line is coupled to a row of flash memory cells in the memory array;
an address fault detection array comprising a column of memory cells, wherein each of the plurality of word lines is coupled to a memory cell in the column; and
an analog comparator for comparing a current drawn by the column with a reference current and for indicating a fault if the current drawn by the column exceeds the reference current.

2. The system of claim 1 , wherein the address fault detection array comprises one or more source line transistors that pull one or more columns in the address fault detection array to ground during a power-down operation.

3. The system of claim 1 , wherein each flash memory cell in the memory array is a split gate flash memory cell.

4. The system of claim 1 , wherein each memory cell in the address fault detection array is a split gate flash memory cell.

5. The system of claim 1 , wherein each memory cell in the address fault detection array is a ROM cell.

6. The system of claim 1 , wherein each flash memory cell in the memory array is programmed through a source side hot electron programming mechanism.

7. The system of claim 1 , wherein each memory cell in the address fault detection array is a flash memory cell programmed through a source side hot electron programming mechanism.

8. The system of claim 1 , wherein each flash memory cell in the memory array comprises a floating gate and an erase gate, wherein a top corner of the floating gate protrudes towards an inside corner of the erase gate to enhance erase efficiency.

9. The system of claim 1 , wherein each memory cell in the address fault detection array is a flash memory cell comprising a floating gate and an erase gate, wherein a top corner of the floating gate protrudes towards an inside corner of the erase gate to enhance erase efficiency.

10. The system of claim 1 , wherein for each flash memory cell in the memory array, an erased state in a flash memory cell represents a “1” value and a programmed state in a flash memory cell represents a “0” value.

11. The system of claim 1 , wherein each memory cell in the address fault detection array is a flash memory cell and an erased state in the flash memory cells represents a “1” value and a programmed state in the flash memory cells represents a “0” value.

12. The system of claim 1 , wherein the memory array and the address fault detection array are coupled to different control gate lines, erase gate lines, and source lines.

13. The system of claim 1 , wherein the analog comparator indicates a fault if no rows have been selected.

14. The system of claim 1 , wherein the analog comparator indicates no fault if one and only one row has been selected.

15. The system of claim 1 , wherein the analog comparator indicates a fault if two or more rows have been selected.

16. The system of claim 1 , further comprising a sensing circuit for reading data in the address fault detection array.

17. The system of claim 16 , wherein the sensing circuit is a differential sensing circuit.

18. The system of claim 16 , wherein the sensing circuit is a single ended sensing circuit.

19. The system of claim 17 , wherein each flash memory cell in the memory array is a split gate flash memory cell.

20. The system of claim 18 , wherein each flash memory cell in the memory array is a split gate flash memory cell.

Assignees

• Silicon Storage Tech Inc

Inventors

• Tran Hieu Van
• Liu Xian
• Do Nhan

Classifications

• H10D30/683

  programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling · CPC title

• H10D30/0411

  of FETs having floating gates · CPC title

• H10D30/6892

  having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate · CPC title

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title

• G11C2029/1204

  Bit line control · CPC title