Redundancy schemes for memory cell repair

Patent metadata

Field	Value
Publication number	US-9911510-B1
Application number	US-201615288832-A
Country	US
Kind code	B1
Filing date	Oct 7, 2016
Priority date	Oct 7, 2016
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

Various implementations described herein are directed to an integrated circuit having a memory cell array with multiple rows of memory cells including at least one redundant row of memory cells. The memory cell array may be partitioned into multiple regions of memory cells including a first region of memory cells corresponding to a first part of the redundant row of memory cells and a second region of memory cells corresponding to a second part of the redundant row of memory cells. The integrated circuit may include wordline driver circuitry coupled to the first and second regions of memory cells and their corresponding first and second parts of the redundant row of memory cells. In some instances, the integrated circuit may include row shift circuitry coupled to the first and second regions of memory cells and their corresponding first and second parts of the redundant row of memory cells.

First claim

What is claimed is:

1. An integrated circuit, comprising:
an array of memory cells arranged in multiple columns and multiple rows,
wherein at least one of the multiple rows comprises a redundant row of memory cells, and
wherein the array of memory cells is subdivided into multiple sections of memory cells including a first section of memory cells having a first portion of the redundant row of memory cells and a second section of memory cells having a second portion of the redundant row of memory cells,
a first plurality of wordline drivers coupled to the first section of memory cells and the first portion of the redundant row of memory cells, wherein the first plurality of wordline drivers has first shifting logic for shifting a first defective row of memory cells from the first section of memory cells to the first portion of the redundant row of memory cells; and
a second plurality of wordline drivers coupled to the second section of memory cells and the second portion of the redundant row of memory cells, wherein the second plurality of wordline drivers has second shifting logic for shifting a second defective row of memory cells from the second section of memory cells to the second portion of the redundant row of memory cells.

2. The integrated circuit of claim 1 , wherein the first section of memory cells is separate and operates independently from the second section of memory cells.

3. The integrated circuit of claim 1 , wherein each wordline driver of the first plurality of wordline drivers is separate and operates independently from each wordline driver of the second plurality of wordline drivers.

4. The integrated circuit of claim 1 , wherein the first shifting logic is separate and operates independently from the second shifting logic.

5. The integrated circuit of claim 1 , wherein the first plurality of wordline drivers is arranged in a first column adjacent to the first section of memory cells and the first portion of the redundant row of memory cells, and wherein each wordline driver of the first plurality of wordline drivers separately accesses one row of memory cells in the first section of memory cells.

6. The integrated circuit of claim 1 , wherein the second plurality of wordline drivers is arranged in a second column adjacent to the second section of memory cells and the second portion of the redundant row of memory cells, and wherein each wordline driver of the second plurality of wordline drivers separately accesses one row of memory cells in the second section of memory cells.

7. The integrated circuit of claim 1 , wherein the first and second sections of memory cells comprise left and right sections of memory cells, and wherein the first and second portions of the redundant row of memory cells comprise left and right portions of the redundant row of memory cells.

8. The integrated circuit of claim 1 , wherein the first and second sections of memory cells comprise upper and lower sections of memory cells.

9. The integrated circuit of claim 8 , wherein:
the redundant row of memory cells comprises an upper redundant row of memory cells corresponding to the upper section of memory cells, and
at least one other of the multiple rows comprises a lower redundant row of memory cells corresponding to the lower section of memory cells.

10. The integrated circuit of claim 9 , wherein:
the first shifting logic shifts the first defective row of memory cells from the upper section of memory cells to the upper redundant row of memory cells, and
the second shifting logic shifts the second defective row of memory cells from the lower section of memory cells to the lower redundant row of memory cells.

11. An integrated circuit, comprising:
a memory cell array having multiple rows of memory cells including at least one redundant row of memory cells,
wherein the memory cell array is partitioned into multiple regions of memory cells including a first region of memory cells corresponding to a first part of the redundant row of memory cells and a second region of memory cells corresponding to a second part of the redundant row of memory cells that is different than the first part;
wordline driver circuitry coupled to the first and second regions of memory cells and their corresponding first and second parts of the redundant row of memory cells; and
row shift circuitry coupled to the first and second regions of memory cells and their corresponding first and second parts of the redundant row of memory cells.

12. The integrated circuit of claim 11 , wherein:
the wordline driver circuitry comprises a first wordline driver circuit that controls access to each row of memory cells in the first region of memory cells, and
the row shift circuitry comprises a first row shift circuit that controls shifting of at least one row of memory cells from the first region of memory cells to the first part of the redundant row of memory cells.

13. The integrated circuit of claim 12 , wherein:
the wordline driver circuitry comprises a second wordline driver circuit that controls access to each row of memory cells in the second region of memory cells, and
the row shift circuitry comprises a second row shift circuit that controls shifting of at least one row of memory cells from the second region of memory cells to the second part of the redundant row of memory cells.

14. The integrated circuit of claim 11 , wherein:
the multiple regions of memory cells include a third region of memory cells corresponding to a third part of the redundant row of memory cells,
the wordline driver circuitry is coupled to the third region of memory cells and its corresponding third part of the redundant row of memory cells, and
the row shift circuitry is coupled to the third region of memory cells and its corresponding third part of the redundant row of memory cells.

15. The integrated circuit of claim 14 , wherein:
the wordline driver circuitry comprises a third wordline driver circuit that controls access to each row of memory cells in the third region of memory cells, and
the row shift circuitry comprises a third row shift circuit that controls shifting of at least one row of memory cells from the third region of memory cells to the third part of the redundant row of memory cells.

16. The integrated circuit of claim 11 , wherein:
the multiple regions of memory cells include a fourth region of memory cells corresponding to a fourth part of the redundant row of memory cells,
the wordline driver circuitry is coupled to the fourth region of memory cells and its corresponding fourth part of the redundant row of memory cells, and
the row shift circuitry is coupled to the fourth region of memory cells and its corresponding fourth part of the redundant row of memory cells.

17. The integrated circuit of claim 16 , wherein:
the wordline driver circuitry comprises a fourth wordline driver circuit that controls access to each row of memory cells in the fourth region of memory cells, and
the row shift circuitry comprises a fourth row shift circuit that controls shifting of at least one row of memory cells from the fourth region of memory cells to the fourth part of the redundant row of memory cells.

18. A method of fabricating an integrated circuit, the method comprising:
providing a memory cell array having multiple rows of memory cells including at least one redundant row of memory cells, wherein the memory cell array is partitioned into multiple regions of memory cells including a first region of memory cells corresponding to a first part of the redundant row of memory cells

Assignees

• Advanced Risc Mach Ltd

Inventors

• Kwon Jungtae
• Kim Young Suk
• Nautiyal Vivek
• Prabhat Pranay
• Bohra Fakhruddin Ali
• Dwivedi Shri Sagar
• Singh Satinderjit
• Gupta Lalit

Classifications

• G11C11/4125

  Cells incorporating circuit means for protecting against loss of information · CPC title

• G11C11/418

  Address circuits · CPC title

• G11C29/76 Primary

  using address translation or modifications · CPC title

• G11C8/04

  using a sequential addressing device, e.g. shift register, counter · CPC title

• G11C11/413

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction · CPC title