Current sensor integrated circuits

Patent metadata

Field	Value
Publication number	US-11519939-B2
Application number	US-202117472769-A
Country	US
Kind code	B2
Filing date	Sep 13, 2021
Priority date	Jan 17, 2020
Publication date	Dec 6, 2022
Grant date	Dec 6, 2022

Abstract

A current sensor integrated circuit (IC) includes a unitary lead frame having at least one first lead having a terminal end, at least one second lead having a terminal end, and a paddle having a first surface and a second opposing surface. A semiconductor die is supported by the first surface of the paddle, wherein the at least one first lead is electrically coupled to the semiconductor die and the at least one second lead is electrically isolated from the semiconductor die. The current sensor IC further includes a first mold material configured to enclose the semiconductor die and the paddle and a second mold material configured to enclose at least a portion of the first mold material, wherein the terminal end of the at least one first lead and the terminal end of the at least one second lead are external to the second mold material.

First claim

What is claimed is:

1. A method of manufacturing a current sensor integrated circuit (IC) comprising:
providing a lead frame comprising at least one first lead having a terminal end, at least one second lead having a terminal end, and a paddle;
attaching a semiconductor die to the paddle;
electrically coupling the at least one first lead to the semiconductor die, wherein the at least one second lead is electrically isolated from the semiconductor die;
molding a first mold material to enclose the semiconductor die and the paddle;
forming the at least one first lead to down set the paddle with respect to the terminal end of the at least one first lead;
molding a second mold material to enclose at least a portion of the first mold material and to expose the terminal end of the at least one first lead and the terminal end of the at least one second lead; and
forming the terminal end of the at least one first lead and the terminal end of the at least one second lead for surface mount attachment.

2. The method of claim 1 wherein providing the lead frame comprises providing the lead frame from a unitary, coplanar lead frame strip.

3. The method of claim 1 wherein the lead frame further comprises at least two dam bars configured to attach the lead frame to one or more lead frames of other current sensor ICs, wherein the method further comprises removing at least one dam bar after molding the first mold material and before forming the at least one first lead to down set the paddle with respect to the terminal end of the at least one first lead.

4. The method of claim 3 further comprising removing at least one dam bar after molding the second mold material.

5. The method of claim 1 wherein molding the second mold material to enclose at least a portion of the first mold material comprises enclosing all surfaces of the first mold material.

6. The method of claim 1 wherein molding the second mold material to enclose at least a portion of the first mold material comprises exposing a surface of the first mold material.

7. The method of claim 1 wherein molding the first mold material to enclose the semiconductor die and the paddle comprises:
placing a portion of the lead frame and the semiconductor die into a first chase comprising a first cavity and a second cavity; and
introducing the first mold material through an opening in the first chase, wherein the at least one first lead extends external to the first mold material at a junction between the first cavity and the second cavity.

8. The method of claim 7 wherein molding the second mold material comprises:
placing the lead frame and the first mold material into a second chase comprising a first cavity and a second cavity; and
introducing the second mold material through an opening in the second chase, wherein the at least one first lead and the at least one second lead extend external to the second mold material at a junction between the first cavity and the second cavity.

Assignees

• Allegro Microsystems Llc

Inventors

• Liu Shixi Louis
• David Paul A
• Milano Shaun D
• Nikam Rishikesh
• Latham Alexander
• Bussing Wade
• Healey Natasha
• El Bacha Georges

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/5449

  not being orthogonal to a side surface of the chip, e.g. fan-out arrangements · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W70/429

  being the outer leads · CPC title

• G01R15/08 Primary

  Circuits for altering the measuring range · CPC title