Vertical three-dimensional semiconductor device and method of making same

Patent metadata

Field	Value
Publication number	US-2016163731-A1
Application number	US-201514960191-A
Country	US
Kind code	A1
Filing date	Dec 4, 2015
Priority date	Dec 5, 2014
Publication date	Jun 9, 2016
Grant date	—

Abstract

The disclosed technology generally relates to semiconductor devices, and more particularly to a vertical three-dimensional semiconductor device and a method for manufacturing such a device. In one aspect, the vertical three-dimensional semiconductor device has a source layer formed over a substrate. A horizontal stack of alternating electrically isolating layers and electrically conductive gate layers are formed over the source layer, wherein one of the electrically isolating layers contacts the source layer. A vertical channel structure extends vertically through the horizontal stack of alternating layers. A drain is formed over the horizontal stack of alternating layers and over the vertical channel structure. The source layer is configured to inject charge carriers into the vertical channel structure, and the metal drain is configured to extract charge carriers from the vertical channel structure. A conductivity of the vertical channel structure is configured to change in response to an electrical bias applied to at least one of the electrically conductive gate layers.

First claim

What is claimed is:

1 . A vertical three-dimensional semiconductor device, comprising:
a source layer formed over a substrate; a horizontal stack of alternating electrically isolating layers and electrically conductive gate layers formed over the source layer, wherein one of the electrically isolating layers closest to the substrate contacts the source layer; a vertical channel structure extending vertically through the horizontal stack of alternating layers; and a metal drain formed over the horizontal stack of alternating layers and contacting the vertical channel structure, wherein the source layer is configured to inject charge carriers into the vertical channel structure, wherein the metal drain is configured to extract charge carriers from the vertical channel structure, and wherein the conductivity of the vertical channel structure is configured to change in response to an electrical bias applied to at least one of the electrically conductive gate layers.

2 . The vertical three-dimensional semiconductor device according to claim 1 , wherein the vertical three dimensional semiconductor device is a junction-less device in which a semiconductor-semiconductor junction is absent.

3 . The vertical three-dimensional semiconductor device according to claim 1 , wherein the vertical channel structure comprises a high mobility semiconductor material.

4 . The vertical three-dimensional semiconductor device according to claim 3 , wherein the high mobility semiconductor material is selected from the group consisting of a III-V compound semiconductor material, a II-VI compound semiconductor material, a IV-IV compound semiconductor material and germanium (Ge).

5 . The vertical three-dimensional semiconductor device according to claim 1 , wherein a dielectric material at least partially covers a side wall of the vertical channel structure.

6 . The vertical three-dimensional semiconductor device according to claim 5 , wherein the dielectric material comprises a plurality of different dielectric layers.

7 . The vertical three-dimensional semiconductor device of claim 1 , wherein the metal drain is formed of a transition metal and/or a noble metal.

8 . The vertical three-dimensional semiconductor device of claim 7 , wherein the metal drain is formed of a metal selected from the group consisting of Cu, Al, Ti, W, Ni, Au, TiN, TaN, TaC, NbN, RuTa, Co, Ta, Mo, Pd, Pt, Ru, Ir and Ag.

9 . The vertical three-dimensional semiconductor device of claim 1 , wherein the source layer is formed of a transition metal and/or a noble metal.

10 . The vertical three-dimensional semiconductor device of claim 9 , wherein the source layer is formed of a a metal selected from the group consisting of Cu, Al, Ti, W, Ni, Au, TiN, TaN, TaC, NbN, RuTa, Co, Ta, Mo, Pd, Pt, Ru, Ir and Ag.

11 . The vertical three-dimensional semiconductor device of claim 1 , wherein each of the electrically conductive gate layers is formed of a transition metal and/or a noble metal.

12 . The vertical three-dimensional semiconductor device of claim 11 , wherein each of the electrically conductive gate layers is formed of a metal selected from a group consisting of Cu, Al, Ti, W, Ni, Au, TiN, TaN, TaC, NbN, RuTa, Co, Ta, Mo, Pd, Pt, Ru, Ir and Ag.

13 . The vertical three-dimensional semiconductor device of claim 1 , wherein each of the electrically isolating layers is formed of an electrically insulating material selected from the group consisting of polysilicon, SiO, SiN, SiON, Al 2 O 3 , AN, MgO and carbides.

14 . The vertical three-dimensional semiconductor device of claim 1 , wherein the vertical three-dimensional semiconductor device is configured as a logic device.

15 . The vertical three-dimensional semiconductor device of claim 1 , wherein the vertical three-dimensional semiconductor device is configured as a memory device, wherein a dielectric material comprising a plurality of dielectric layers at least partially covers a side wall of the vertical channel structure.

16 . The vertical three-dimensional semiconductor device of claim 15 , wherein the dielectric material comprises a tunneling layer surrounding the vertical channel structure, a charge storage layer surrounding the tunneling layer and a charge blocking layer surrounding the charge storage layer.

17 . The vertical three-dimensional semiconductor device of claim 16 , wherein the charge blocking layer includes a stack of layers including a nitride layer interposed between two oxide layers.

18 . The vertical three-dimensional semiconductor device of claim 16 , wherein the dielectric material comprises a high-K dielectric material.

19 . A method of fabricating a vertical three-dimensional semiconductor device, the method comprising:
providing a semiconductor substrate; forming a sacrificial source layer on the substrate; forming on the sacrificial source layer a horizontal stack of alternating electrically isolating layers and sacrificial gate layers, wherein one of the electrically isolating layers closest to the semiconductor substrate contacts the sacrificial source layer; forming a vertical channel structure vertically extending through the horizontal stack of alternating layers; forming a metal drain over the horizontal stack of alternating layers and contacting the vertical channel structure; forming a vertical opening through the horizontal stack of alternating layers and further through the sacrificial source layer, the vertical opening formed at a lateral distance from the vertical channel structure; replacing the sacrificial source layer with a source layer; and replacing the sacrificial conductive gate layers with electrically conductive gate layers.

Assignees

• Imec Vzw

Inventors

• Tan Chi Lim
• Lisoni Reyes Judit Gloria

Classifications

• H10D30/0413

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/025 Primary

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title

• H10D62/832

  being Group IV materials comprising two or more elements, e.g. SiGe · CPC title

• H10D62/112

  for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers · CPC title

• H10D62/86

  being Group II-VI materials, e.g. ZnO · CPC title