Leakage-free implantation-free ETSOI transistors

Patent metadata

Field	Value
Publication number	US-11502171-B2
Application number	US-202017134695-A
Country	US
Kind code	B2
Filing date	Dec 28, 2020
Priority date	Jul 30, 2015
Publication date	Nov 15, 2022
Grant date	Nov 15, 2022

Abstract

A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.

First claim

The invention claimed is:

1. A method for forming a transistor, comprising:
patterning a semiconductor on insulator (SOI) layer of a semiconductor-on-insulator (SOI) substrate, the SOI substrate comprising a base substrate, said semiconductor on insulator (SOI) layer and a buried dielectric therebetween, the patterning forming a device channel and defining openings for source and drain regions through the semiconductor on insulator (SOI) layer;
depositing a II-VI semiconductor composition layer on the buried dielectric within the openings in the semiconductor on insulator (SOI) layer to form source and drain regions at opposing positions relative to the device channel, the buried dielectric being a continuous layer that extends from an outside edge of the source region continuously across the device channel to an outside edge of the drain region; and
planarizing the II-VI semiconductor composition layer to form the source and drain regions at a same thickness as the semiconductor on insulator (SOI) layer.

2. The method of claim 1 , further comprising forming a gate structure over the device channel.

3. The method of claim 1 , wherein depositing II-VI semiconductor composition layer includes atomic layer deposition.

4. The method of claim 3 , wherein doping is performed during formation of the II-VI semiconductor composition layer to provide an n-type conductivity.

5. The method as recited in claim 1 , wherein the II-VI semiconductor composition layer includes ZnO.

6. The method as recited in claim 5 , wherein the ZnO is Al-doped.

7. The method as recited in claim 1 , wherein the II-VI semiconductor composition layer includes an amorphous phase.

8. The method as recited in claim 1 , further comprising doping the source and drain regions by implantation.

9. The method as recited in claim 8 , wherein doping the source and drain regions by implantation is performed after forming the gate structure.

10. The method as recited in claim 1 , further comprising forming contacts to the source and drain regions.

11. The method of claim 1 , wherein the thickness of the II-VI semiconductor composition layer does not require recrystallization to provide a crystalline structure.

12. The method of claim 1 , wherein the II-VI semiconductor composition is selected from the group consisting of ZnO, ZnS, ZnSe, CdS, CdTe and combinations thereof.

13. The method of claim 1 , wherein the II-VI semiconductor composition comprises aluminum doped zinc oxide (ZnO:Al).

14. The method of claim 1 , wherein the semiconductor on insulator (SOI) layer comprising a type IV semiconductor.

15. The method of claim 1 , wherein the semiconductor on insulator (SOI) layer comprises a type III-V semiconductor.

16. A method for forming a transistor, comprising:
Forming a material stack of a semiconductor layer on a dielectric layer, wherein the dielectric layer is positioned between the semiconductor layer and a base semiconductor substrate;
patterning the semiconductor layer to defining openings for source and drain regions through the semiconductor layer, wherein a remaining portion of the semiconductor layer between the openings provides a channel region;
depositing a II-V semiconductor composition layer on the dielectric layer within the openings in the semiconductor layer to form source and drain regions at opposing positions relative to the channel region, the dielectric layer being a continuous layer that extends from an outside edge of the source region continuously across the channel to an outside edge of the drain region; and
planarizing the II-VI semiconductor composition layer to form the source and drain regions at a same thickness as the semiconductor on insulator (SOI) layer.

17. The method of claim 16 , wherein depositing II-VI semiconductor composition layer includes atomic layer deposition.

18. The method of claim 17 , wherein doping is performed during formation of the II-VI semiconductor composition layer to provide an n-type conductivity.

Assignees

• IBM

Inventors

• De Souza Joel P
• Fogel Keith E
• Kim Jeehwan
• Sadana Devendra K

Classifications

• H10P14/3424

  being Group IIB-VIA materials · CPC title

• H10P14/3402

  characterised by the chemical composition · CPC title

• H10P30/202

  characterised by the semiconductor materials · CPC title

• H10P14/3451

  Structure · CPC title

• H10P14/3442

  N-type · CPC title