Transistor with reduced parasitic capacitance and access resistance of the source and drain, and method of fabrication of the same

Patent metadata

Field	Value
Publication number	US-9337350-B2
Application number	US-201213727104-A
Country	US
Kind code	B2
Filing date	Dec 26, 2012
Priority date	Dec 27, 2011
Publication date	May 10, 2016
Grant date	May 10, 2016

Abstract

A transistor includes an active layer forming a channel for the transistor, an insulating layer disposed facing a lower face of the active layer, a gate turned toward an upper face of the active layer and a source and a drain disposed on both sides of the gate. At least one among the source and the drain extends at least partly through the active layer and into the insulating layer.

First claim

The invention claimed is:

1. A method of fabrication of a transistor, comprising:
preparing a stack of layers provided with at least one substrate overlaid by an insulating layer and by an active layer, a first portion of the active layer being configured to form a channel for the transistor, and a second portion of the active layer and a third portion of the active layer being separated from each other and from the first portion; and
preparing a source and a drain, wherein said preparing comprises:
depositing a protective layer covering at least the active layer,
forming openings through the protective layer and the active layer to expose the insulating layer at zones intended to form the source and the drain, the protective layer forming at least a first two walls above one of the zones intended to form the source and at least a second two walls above another of the zones intended to form the drain;
forming cavities in the insulating layer at a bottom of the openings, the cavities extending under the at least the first two walls and extending under the at least the second two walls; and
filling the cavities by a semiconductor material, the protective layer being preserved during the filling of the cavities,

wherein the source and the drain do not extend over an upper face of the first portion of the active layer, the second portion of the active layer, and the third portion of the active layer, and
wherein the source contacts at least two first side surfaces and at least two first bottom surfaces of the active layer, and the drain contacts at least two second side surfaces and at least two second bottom surfaces of the active layer.

2. The method according to claim 1 , wherein the forming of the cavities in the insulating layer is performed so that a depth of said cavities in a direction perpendicular to a plane of the at least one substrate is between one nanometer and a thickness equal to another thickness of the insulating layer less two nanometers, the another thickness being taken from a lower face of the active layer and in a direction perpendicular to the plane of the at least one substrate.

3. The method according to claim 2 , wherein the active layer is made of the semiconductor material and the filling of the cavities is achieved by epitaxy of the active layer.

4. The method according to claim 3 , wherein the forming of the cavities takes place in such a way that each bottom of the cavities is situated in the insulating layer and such that lateral extremities of the cavities are distant from a vertical extension of sidewalls of a gate.

5. The method according to claim 4 , wherein silicidation of contacts is performed at the source and the drain.

6. The method according to claim 1 , wherein the protective layer is preserved in the course of all of the steps after the depositing the protective layer.

7. The method according to claim 1 , additionally comprising, after the filling of the cavities by the semiconductor material:
removing the protective layer;
depositing at least one electrically insulating layer;
opening contact zones at least at the source and the drain through said least one electrically insulating layer.

8. The method according to claim 1 , wherein the source and the drain are doped either in situ during the filling of the cavities, or by ion implantation after the filling of the cavities.

9. The method according to claim 1 , wherein the source and the drain are subjected to diffusion annealing.

10. The method according to claim 1 , wherein the stack of layers comprising the at least one substrate, the insulating layer, and the active layer is a substrate of semiconductor on insulator type.

11. The method according to claim 1 , wherein the material constituting the protective layer is carbon-doped silicon oxide (SiOCH) or is amorphous carbon (APF).

12. The method according to claim 1 , wherein the preparing the source and the drain is performed after forming a control gate of the transistor or before forming a control gate of the transistor, the control gate being formed such that it is overlying the active layer.

13. A transistor, comprising:
an active layer, a first portion of the active layer forming a channel for the transistor, and a second portion of the active layer and a third portion of the active layer being separated from each other and from the first portion;
an insulating layer disposed facing a lower face of the active layer;
a gate facing an upper face of the active layer;
a protective layer covering the active layer and the gate;
openings that extend through the protective layer and through the active layer, said openings in the protective layer being aligned with said openings in the active layer; and
a source and a drain disposed on both sides of the gate,
wherein at least one among the source and the drain extends at least partly through the openings in the active layer and into cavities of the insulating layer disposed at least partly under the openings, in such a way as to fill the cavities entirely,
wherein the protective layer includes at least a first two walls above the source and at least a second two walls above the drain,
wherein the cavities extend under the at least the first two walls and extend under the at least the second two walls,
wherein the source and the drain do not extend over the upper face of the first portion of the active layer, the second portion of the active layer, and the third portion of the active layer, and
wherein the source contacts at least two first side surfaces and at least two first bottom surfaces of the active layer, and the drain contacts at least two second side surfaces and at least two second bottom surfaces of the active layer.

14. The transistor according to claim 13 , wherein the at least one among the source and the drain has a thickness of between 1 nanometer and a thickness equal to another thickness of the insulating layer less two nanometers, the another thickness being taken in a direction perpendicular to a plane of a substrate on which the active layer and the insulating layer are disposed.

15. The transistor according to claim 14 , wherein an upper face of the at least one among the source and the drain, taken in a direction parallel to the plane of the substrate, is disposed entirely underneath a lower face of the gate.

Assignees

• Commissariat Energie Atomique
• Commissariat Energie Atomique

Inventors

• Posseme Nicolas
• Grenouillet Laurent
• Le Tiec Yannick
• Vinet Maud

Classifications

• H10D62/021 Primary

  Forming source or drain recesses by etching e.g. recessing by etching and then refilling · CPC title

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title

• H10D30/0323

  comprising monocrystalline silicon · CPC title

• H10D30/021

  of FETs having insulated gates [IGFET] · CPC title

• H10D30/6713

  characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes · CPC title