Leakage-free implantation-free ETSOI transistors

Patent metadata

Field	Value
Publication number	US-10937864-B2
Application number	US-201715453089-A
Country	US
Kind code	B2
Filing date	Mar 8, 2017
Priority date	Jul 30, 2015
Publication date	Mar 2, 2021
Grant date	Mar 2, 2021

Abstract

A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
an extremely thin semiconductor-on-insulator (ETSOI) substrate having a base substrate, at least first, second and third thin semiconductor layer portions and a buried dielectric therebetween, the first, second and third semiconductor layer portions each including a first material;
a device channel corresponding to the first thin semiconductor layer portion;
source and drain regions on the buried dielectric having upper surfaces colinear with upper surfaces of at least the first, second and third thin semiconductor layer portions, the source and drain regions including:
a first source/drain region between a first sidewall of the device channel and a sidewall of the second thin semiconductor layer portion; and
a second source/drain region between a second sidewall of the device channel and a sidewall of the third thin semiconductor layer portion;

the source and drain regions including an n-type oxide material different from the first material; and
a gate structure formed over the device channel.

2. The semiconductor device as recited in claim 1 , wherein the n-type material includes ZnO.

3. The semiconductor device as recited in claim 2 , wherein the ZnO is Al-doped.

4. The semiconductor device as recited in claim 1 , wherein the n-type material includes a II-VI material.

5. The semiconductor device as recited in claim 1 , wherein the source and drain regions have a substantially same thickness as the thin semiconductor layer portions.

6. The semiconductor device as recited in claim 1 , wherein the thin semiconductor layer includes monocrystalline silicon (Si).

7. The semiconductor device as recited in claim 1 , wherein the thin semiconductor layer includes a III-V material.

8. A semiconductor device, comprising:
an extremely thin semiconductor-on-insulator (ETSOI) substrate having a base substrate, at least first, second and third thin semiconductor layer portions and a buried dielectric therebetween, the first, second and third thin semiconductor layer portions each including a III-V material;
a device channel corresponding to the first thin semiconductor layer portion;
aluminum doped zinc oxide (ZnO:Al) deposited on the buried dielectric corresponding to source and drain regions each adjacent to a respective sidewall of the device channel and a sidewall of a respective one of the second and third thin semiconductor layer portions, the source and drain regions being coplanar with at least the first, second and third thin semiconductor layer portions; and
a gate structure formed over the device channel.

9. The semiconductor device as recited in claim 8 , wherein the source and drain regions have a substantially same thickness as the thin semiconductor layer portions.

10. The semiconductor device as recited in claim 8 , wherein the aluminum doped zinc oxide includes an amorphous phase.

11. The semiconductor device as recited in claim 8 , wherein the source and drain regions include a first source/drain region disposed between a first sidewall of the device channel and a sidewall of the second thin semiconductor layer portion, and a second source/drain region disposed between a second sidewall of the device channel and a sidewall of the third thin semiconductor layer portion.

12. A semiconductor device, comprising:
an extremely thin semiconductor-on-insulator (ETSOI) substrate having a base substrate, at least first, second and third thin semiconductor layer portions and a buried dielectric therebetween, the first, second and third thin semiconductor layer portions each including monocrystalline silicon (Si);
a device channel corresponding to the first thin semiconductor layer portion;
source and drain regions on the buried dielectric having upper surfaces colinear with upper surfaces of at least the first, second and third thin semiconductor layer portions, the source and drain regions including:
a first source/drain region between a first sidewall of the device channel and a sidewall of the second thin semiconductor layer portion; and
a second source/drain region between a second sidewall of the device channel and a sidewall of the third thin semiconductor layer portion;
the source and drain regions including aluminum doped zinc oxide (ZnO:Al); and
a gate structure formed over the device channel.

13. The semiconductor device as recited in claim 12 , wherein the source and drain regions have a substantially same thickness as the extremely thin semiconductor layer portions.

14. The semiconductor device as recited in claim 12 , wherein the aluminum doped zinc oxide (ZnO:Al) includes an amorphous phase.

Assignees

• IBM

Inventors

• De Souza Joel P
• Fogel Keith E
• Kim Jeehwan
• Sadana Devendra K

Classifications

• H10P14/3424

  being Group IIB-VIA materials · CPC title

• H10P14/3402

  characterised by the chemical composition · CPC title

• H10P30/202

  characterised by the semiconductor materials · CPC title

• H10P14/3451

  Structure · CPC title

• H10P14/3442

  N-type · CPC title