Gate all around I/O engineering

Patent metadata

Field	Value
Publication number	US-11450759-B2
Application number	US-202017037941-A
Country	US
Kind code	B2
Filing date	Sep 30, 2020
Priority date	Oct 2, 2019
Publication date	Sep 20, 2022
Grant date	Sep 20, 2022

Abstract

Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-κ layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-κ layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.

First claim

What is claimed is:

1. A method of manufacturing an electronic device, the method comprising:
forming alternating layers of silicon (Si) and silicon germanium (SiGe) on a substrate;
patterning and etching the alternating layers of silicon and silicon germanium to expose at least one side wall of the silicon layer and at least one sidewall of the silicon germanium layer;
selectively etching the silicon germanium layer to form an opening;
forming a thermal oxide layer on the silicon layer through the opening;
passivating the thermal oxide layer to form a passivated thermal oxide layer;
depositing a low-κ layer on the passivated thermal oxide layer through the opening; and
densifying the low-κ layer to form a densified low-κ layer.

2. The method of claim 1 , wherein the alternating layers of silicon and silicon germanium are formed by a selective epitaxial growth (SEG) process.

3. The method of claim 1 , wherein forming the thermal oxide layer comprises an enhanced in situ steam generation (eISSG) process.

4. The method of claim 1 , wherein the thermal oxide layer has a thickness in a range of about 3 to about 10 Å.

5. The method of claim 1 , wherein the low-κ layer has a thickness less than about 2 nm.

6. The method of claim 5 , wherein the low-κ layer has a thickness less than about 1.5 nm.

7. The method of claim 1 , wherein in the thermal oxide layer comprises silicon oxide.

8. The method of claim 1 , wherein the low-κ layer comprises one or more of silicon oxide, silicon oxycarbide, silicon oxynitride, SiCOH, SiCONH, or aluminum oxide.

9. The method of claim 1 , wherein the low-κ layer has a dielectric constant in a range of about 1 to about 6.

10. The method of claim 1 , wherein depositing the low-κ layer on the passivated thermal oxide layer comprises an atomic layer deposition process.

11. The method of claim 10 , wherein the atomic layer deposition process is a plasma enhanced atomic layer deposition process.

12. The method of claim 1 , wherein passivating the thermal oxide layer comprises one or more of an annealing process or a plasma treatment process.

13. The method of claim 12 , wherein passivating the thermal oxide layer comprises annealing the thermal oxide layer with one or more of RTH 2 or RTN 2 .

14. The method of claim 12 , wherein passivating the thermal oxide layer comprises a plasma treatment process with one or more of DPHe, DPH 2 , DPN 2 , or DPNH 3 .

15. The method of claim 1 , wherein densifying the low-κ layer comprises annealing the low-κ layer with one or more of RTH 2 or RTN 2 .

16. The method of claim 1 , wherein densifying the low-κ layer comprises a plasma treatment process with one or more of DPHe, DPH 2 , DPN 2 , or DPNH 3 .

17. The method of claim 1 , wherein the electronic device is a gate-all-around (GAA) transistor.

18. The method of claim 17 , wherein the gate-all-around transistor comprises a source region having a source and a source contact, the source region on a top surface of the substrate; a drain region having a drain and a drain contact, the drain region on the top surface of the substrate; a channel located between the source and the drain and having an axis that that is substantially orthogonal to the top surface of the substrate; a gate enclosing the channel between the source region and the drain region; the thermal oxide layer overlying and in contact with one or more of the gate, the source contact, or the drain contact; and the low-κ layer overlying the thermal oxide layer.

19. A non-transitory computer readable medium including instructions, that, when executed by a controller of a processing chamber, causes the processing chamber to perform operations of:
forming alternating layers of silicon and silicon germanium on a substrate;
patterning and etching the alternating layers of silicon and silicon germanium to expose at least one sidewall;
selectively etching the silicon germanium layers;
performing an enhanced in situ steam generation process to form a thermal oxide layer on the silicon layer;
passivating the thermal oxide layer;
depositing a low-κ layer; and
densifying and/or passivating the low-κ layer.

Assignees

• Applied Materials Inc

Inventors

• Hung Steven C H
• Colombeau Benjamin
• Lo Andy
• Lee Byeong Chan
• Swenberg Johanes F
• Guarini Theresa Kramer
• Bevan Malcolm J

Classifications

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P14/6322

  Formation by thermal treatments (formation by plasma treatment H10P14/6319) · CPC title

• H10P14/6309

  of silicon in uncombined form, i.e. pure silicon · CPC title

• H10P14/662 Primary

  Laminate layers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers H10P14/6508, H10P14/6548) · CPC title

• H10P72/0466

  characterised by the construction of the load-lock chamber · CPC title