Semiconductor devices including decoupling capacitors

Patent metadata

Field	Value
Publication number	US-11450600-B2
Application number	US-202017004768-A
Country	US
Kind code	B2
Filing date	Aug 27, 2020
Priority date	May 12, 2020
Publication date	Sep 20, 2022
Grant date	Sep 20, 2022

Abstract

Methods of forming decoupling capacitors in interconnect structures formed on backsides of semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a device includes a device layer including a first transistor; a first interconnect structure on a front-side of the device layer; a second interconnect structure on a backside of the device layer, the second interconnect structure including a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a first conductive layer including a first conductive line electrically connected to the source/drain region of the first transistor through the contact; and a second dielectric layer adjacent the first conductive line, the second dielectric layer including a material having a k-value greater than 7.0, a first decoupling capacitor including the first conductive line and the second dielectric layer.

First claim

What is claimed is:

1. A device comprising:
a device layer comprising a first transistor, the first transistor comprising a first source/drain region and a second source/drain region;
a first interconnect structure on a front-side of the device layer, the first interconnect structure comprising a first source/drain contact physically and electrically coupled to a front-side of the first source/drain region; and
a second interconnect structure on a backside of the device layer, the second interconnect structure comprising:
a first dielectric layer on the backside of the device layer;
a second source/drain contact extending through the first dielectric layer to the second source/drain region, wherein the second source/drain contact is physically and electrically coupled to a backside of the second source/drain region;
a first conductive layer comprising a first conductive line electrically connected to the second source/drain region of the first transistor through the second source/drain contact; and
a second dielectric layer adjacent the first conductive line, the second dielectric layer comprising a material having a k-value greater than 7.0, wherein a first decoupling capacitor comprises the first conductive line and the second dielectric layer.

2. The device of claim 1 , wherein the first conductive line is a power supply line or an electrical ground line.

3. The device of claim 1 , wherein the first conductive layer further comprises a second conductive line, wherein the first conductive line is a power supply line, wherein the second conductive line is an electrical ground line, and wherein the second dielectric layer is directly between and in physical contact with the first conductive line and the second conductive line.

4. The device of claim 1 , wherein the second interconnect structure further comprises a second conductive layer, the second conductive layer comprising a second conductive line, wherein the first conductive line is a power supply line, wherein the second conductive line is an electrical ground line, and wherein the second dielectric layer is directly between and in physical contact with the first conductive layer and the second conductive layer in a direction perpendicular to a major surface of the device layer.

5. The device of claim 1 , wherein the second dielectric layer comprises a metal oxide material.

6. The device of claim 1 , wherein the first interconnect structure comprises a second decoupling capacitor.

7. The device of claim 1 , wherein the device layer comprises a second transistor, wherein the second transistor is coupled to the first transistor through the first interconnect structure.

8. A device comprising:
a first transistor structure and a second transistor structure in a device layer;
a front-side interconnect structure on a front-side of the device layer, the first transistor structure being electrically coupled to the second transistor structure through the front-side interconnect structure, the front-side interconnect structure comprising a gate contact physically and electrically coupled to a front-side of a gate structure of the first transistor structure; and
a backside interconnect structure on a backside of the device layer, the backside interconnect structure comprising:
a first dielectric layer on the backside of the device layer;
a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure, wherein the first contact is physically and electrically coupled to a backside of the source/drain region, the backside of the source/drain region facing a direction opposite the front-side of the gate structure;
a decoupling capacitor;
a power supply line; and
an electrical ground line.

9. The device of claim 8 , wherein the decoupling capacitor comprises a dielectric material extending between the power supply line and the electrical ground line in a direction parallel to a major surface of the device layer, wherein the dielectric material is in physical contact with the power supply line and the electrical ground line.

10. The device of claim 9 , wherein the dielectric material comprises a material having a k-value greater than 7.0.

11. The device of claim 8 , wherein the decoupling capacitor comprises a dielectric material extending between the power supply line and the electrical ground line in a direction perpendicular to a major surface of the device layer, wherein the dielectric material is in physical contact with the power supply line and the electrical ground line.

12. The device of claim 8 , wherein the first transistor structure is an n-type transistor structure, wherein the first transistor structure is electrically coupled to the electrical ground line, wherein the second transistor structure is a p-type transistor structure, and wherein the second transistor structure is electrically coupled to the power supply line.

13. The device of claim 8 , wherein the power supply line is electrically coupled to the source/drain region through the first contact, wherein the backside interconnect structure further comprises a second contact extending through the first dielectric layer and electrically coupled to a second source/drain region of the second transistor structure, and wherein the electrical ground line is electrically coupled to the second source/drain region through the second contact.

14. The device of claim 13 , wherein the first transistor structure is electrically coupled to the front-side interconnect structure through a third source/drain region, and wherein the second transistor structure is electrically coupled to the front-side interconnect structure through a fourth source/drain region.

15. A device comprising:
a first transistor, the first transistor comprising a gate structure and a source/drain region adjacent the gate structure;
a first interconnect structure over a backside of the first transistor, the first interconnect structure comprising:
a first dielectric layer over the backside of the first transistor;
a backside via extending through the first dielectric layer, wherein the backside via is physically and electrically coupled to a backside of the source/drain region of the first transistor; and
a decoupling capacitor over the backside via and the first dielectric layer, the decoupling capacitor comprising:
a second dielectric layer over the backside via and the first dielectric layer, the second dielectric layer comprising a dielectric material having a k-value greater than 7.0;
a first conductive line in the second dielectric layer, wherein the first conductive line is electrically coupled to the backside via, wherein the first conductive line is further electrically coupled to a power supply line or an electrical ground line; and

a second conductive line in the second dielectric layer; and

a second interconnect structure over a front-side of the first transistor opposite the first interconnect structure, the second interconnect structure comprising a gate contact physically and electrically coupled to a front-side of the gate structure, wherein the front-side of the gate structure is opposite the backside of the source/drain region.

16. The device of claim 15 , wherein the second interconnect structure comprises a second decoupling capacitor.

17. The device of claim 16 , wherein the second interconnect structure electrically couples the first transistor to a second transistor.

18. The device of claim 17 , wherein a second source/drain region of the second transistor is electrically coupled to the

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang yu-xuan
• Chen Hou-Yu
• Tsai Ching-Wei
• Cheng Kuan-Lun
• Chen Chung-Hui

Classifications

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/086

  involving buried masks · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/496 Primary

  Capacitor integral with wiring layers · CPC title