Semiconductor memory device performing read retry mode and operating method of the same

Patent metadata

Field	Value
Publication number	US-9293209-B2
Application number	US-201313799523-A
Country	US
Kind code	B2
Filing date	Mar 13, 2013
Priority date	Aug 29, 2012
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

An operating method of a semiconductor memory device includes performing a first read operation on main cells of a first page with an initial read voltage, performing a second read operation on the main cells of the first page with a read voltage corresponding to a read retry number when the number of error bits generated as results of performing the first read operation exceeds the number of error-correctable bits, and storing the read retry number in spare cells of the first page while the second read operation is performed, and repeatedly performing the second read operation and repeatedly storing the read retry number until the number of error bits generated as results of performing the second read operation becomes the number of error-correctable bits or less.

First claim

What is claimed is:

1. An operating method of a semiconductor memory device, comprising:
performing a first read operation on main cells of a first page with an initial read voltage;
performing a second read operation on the main cells of the first page with a read voltage corresponding to a read retry number when a number of error bits generated as results of performing the first read operation exceeds a number of error-correctable bits;
storing the read retry number in spare cells of the first page while the second read operation is performed; and
repeating the performing the second read operation and the storing the read retry number until a number of error bits generated as results of performing the second read operation becomes the number of error-correctable bits or less.

2. The operating method of claim 1 , further comprising performing a read operation on main cells of a second page with a read voltage corresponding to a read retry number stored after repeatedly performing the second read operation and repeatedly storing the read retry number.

3. The operating method of claim 1 , further comprising:
reading a read retry number stored in the spare cells of the first page; and
performing a read operation on main cells of a second page with a read voltage corresponding to the read retry number.

4. The operating method of claim 3 , wherein reading the read retry number stored in the spare cells of the first page is performed when the semiconductor memory device is powered on.

5. The operating method of claim 1 , wherein storing the read retry number in the spare cells of the first page while the second read operation is performed includes supplying a lower voltage than the read voltage to bit lines of the spare cells to store the read retry number in the spare cells.

6. An operating method of a semiconductor memory device, comprising:
performing a read operation on spare cells of a first page with a reference read voltage to read a read retry number from the spare cells;
performing a read operation on main cells of the first page with a first read voltage determined based on the read retry number to read data from the main cells;
updating the read retry number when a number of error bits of the data exceeds a number of error-correctable bits; and
performing a read operation on the main cells of the first page with a second read voltage determined based on the updated read retry number to read the data from the main cells.

7. The operating method of claim 6 , wherein storing the updated read retry number in the spare cells of the first page is performed while the data is read with the second read voltage determined based on the updated read retry number.

8. The operating method of claim 7 , wherein a voltage lower than the second read voltage is supplied to bit lines of the spare cells of the first page while the data is read with the second read voltage determined based on the updated read retry number, to store the updated read retry number in the spare cells of the first page while the data is read with the second read voltage determined based on the updated read retry number.

9. The operating method of claim 6 , further comprising repeatedly updating the read retry number and repeatedly reading the data with a read voltage determined based on the updated read retry number until the number of error bits of the data becomes the number of error-correctable bits or less.

10. The operating method of claim 9 , further comprising performing a read operation on main cells of a second page with a read voltage determined by repeatedly updating the read retry number and repeatedly reading the data with the read voltage determined according to the updated read retry number.

11. The operating method of claim 9 , wherein the updated read retry number is stored in the spare cells of the first page while the data is read with the read voltage determined based on the updated read retry number.

12. The operating method of claim 11 , wherein a voltage lower than the read voltage is supplied to bit lines of the spare cells of the first page while the data is read with the read voltage determined based on the updated read retry number, to store the updated read retry number in the spare cells of the first page while the data is read with the read voltage determined based on the updated read retry number.

13. The operating method of claim 6 , wherein reading the read retry number of the first page is performed when the semiconductor memory device is powered on.

14. A semiconductor memory device, comprising:
a memory array including main cells for storing data and spare cells for storing a read retry number;
a page buffer configured to read the data or the read retry number;
an error corrector configured to correct an error of the read data; and
a voltage supplier configured to supply a read voltage set based on the read retry number to the memory array,
wherein when the error corrector determines that the read data is failed, the voltage supplier updates the read retry number to reset the read voltage, and
the page buffer stores the updated read retry number in the spare cells.

15. The semiconductor memory device of claim 14 , wherein the voltage supplier supplies the reset read voltage to the memory array, and
the page buffer reads the data with the reset read voltage.

16. The semiconductor memory device of claim 15 , wherein the page buffer stores the updated read retry number in the spare cells while reading the data with the reset read voltage.

17. The semiconductor memory device of claim 16 , wherein the page buffer supplies a voltage lower than the reset read voltage to bit lines of the spare cells to store the updated read retry number in the spare cells while reading the data with the reset read voltage.

18. The semiconductor memory device of claim 14 , wherein the page buffer stores an updated read retry number in the spare cells when the error corrector determines that the read data is passed.

19. The semiconductor memory device of claim 18 , wherein the page buffer reads the read retry number when the semiconductor memory device is powered on.

20. The semiconductor memory device of claim 14 , wherein, when a number of error bits of the read data exceeds a number of correctable bits, the error corrector determines that the read data is failed and outputs a fail signal to the voltage supplier, and
the voltage supplier updates the read retry number in response to the fail signal.

Assignees

• Sk Hynix Inc

Inventors

• Ahn Jung Ryul
• Baik Seung Hwan

Classifications

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C7/10

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title