Memory devices and their operation having trim registers associated with access operation commands

Patent metadata

Field	Value
Publication number	US-2016155507-A1
Application number	US-201615015424-A
Country	US
Kind code	A1
Filing date	Feb 4, 2016
Priority date	Dec 21, 2012
Publication date	Jun 2, 2016
Grant date	—

Abstract

Methods including performing an access operation on a memory device using trims corresponding to trim settings, receiving a command to suspend the access operation, loading updated trim settings into a particular trim register of the memory device, setting updated trims for the access operation in response to the updated trim settings of the particular trim register, and resuming the access operation using the updated trims. Apparatus including an external controller and a memory device having an internal controller configured to set trims in response to trim settings and to perform an access operation on an array of memory cells using the trims in response to receiving the access command, wherein the external controller is configured to select trim settings corresponding to a desired mode of operation, and to transmit the selected trim settings to the memory device

First claim

What is claimed is:

1 . A method, comprising:
performing an access operation on a memory device using trims corresponding to trim settings; receiving a command to suspend the access operation; loading updated trim settings into a particular trim register of the memory device; setting updated trims for the access operation in response to the updated trim settings of the particular trim register; and resuming the access operation using the updated trims.

2 . The method of claim 1 , further comprising:
receiving a command for the access operation; and setting the trims in response to the trim settings prior to performing the access operation.

3 . The method of claim 2 , further comprising loading a trim register with the trim settings prior to setting the trims.

4 . The method of claim 3 , further comprising loading the trim register with the trim settings in response to receiving the command for the access operation.

5 . The method of claim 1 , further comprising storing the trim settings to the particular trim register in response to receiving the command to suspend the access operation.

6 . The method of claim 1 , wherein resuming the access operation comprises resuming the access operation in response to receiving a command to resume the access operation.

7 . The method of claim 1 , wherein resuming the access operation comprises resuming the access operation in response to completion of an operation initiated after receiving the command to suspend the access operation.

8 . A method, comprising:
receiving a command to perform an access operation on a grouping of memory cells of an array of memory cells of a memory device; setting trims in response to trim settings; performing the access operation on the grouping of memory cells using the trims; receiving a command to suspend the access operation; loading updated trim settings into a particular trim register of the memory device; setting updated trims for the access operation in response to the updated trim settings of the particular trim register; and resuming the access operation using the updated trims in response to a criteria selected from a group consisting of receiving a command to resume the suspended access operation, and completion of an intervening operation performed while the access operation is suspended.

9 . The method of claim 8 , further comprising storing the trim settings to the particular trim register prior to loading the updated trim settings into the particular trim register.

10 . The method of claim 9 , further comprising loading the updated trim settings into the particular trim register in response to a different command received by the memory device.

11 . The method of claim 8 , further comprising loading the updated trim settings into the particular trim register in response to the command to suspend the access operation.

12 . The method of claim 8 , further comprising:
receiving a subsequent command to perform the intervening operation on a different grouping of memory cells of the array of memory cells while the access operation is suspended; and performing the intervening operation on the different grouping of memory cells.

13 . The method of claim 8 , further comprising:
loading a trim register associated with the command to perform the access operation with the trim settings while the memory device is performing a prior access operation a different grouping of memory cells of the array of memory cells.

14 . The method of claim 8 , wherein setting the trims in response to the trim settings comprises setting parameters to be utilized by the memory device to perform the access operation on the grouping of memory cells in response to the trim settings.

15 . The method of claim 14 , wherein setting parameters to be utilized by the memory device to perform the access operation comprises setting at least one parameter selected from a group consisting of voltages to be applied during the access operation, voltage differentials to be utilized during the access operation, and quantities to be utilized during the access operation.

16 . The method of claim 8 , wherein setting the updated trims for the access operation is further in response to the selected criteria for resuming the access operation.

17 . An apparatus, comprising:
an external controller; a memory in communication with the external controller and storing trim settings corresponding to a plurality of modes of operation; and a memory device in communication with the external controller, the memory device comprising:
an array of memory cells;
an internal controller; and
a trim register array comprising a plurality of trim registers;
wherein the internal controller is configured to load trim settings to a trim register of the trim register array in response to a command received from the external controller;
wherein the internal controller is further configured to set trims in response to the trim settings of the trim register in response to receiving an access command associated with the trim settings of the trim register; and
wherein the internal controller is further configured to perform an access operation on the array of memory cells using the trims in response to receiving the access command; and
wherein the external controller is configured, in response to receiving a command from an external device indicative of a desired mode of operation, to select trim settings corresponding to the desired mode of operation, and to transmit the selected trim settings to the memory device.

18 . The apparatus of claim 17 , wherein the external controller is configured to generate a command to the memory device to load the selected trim settings to the trim register of the memory device, wherein the command to the memory device comprises the selected trim settings.

19 . The apparatus of claim 17 , wherein the memory in communication with the external controller is internal to the external controller.

20 . The apparatus of claim 17 , wherein the memory in communication with the external controller is external to the external controller.

Assignees

• Micron Technology Inc

Inventors

• Grunzke Terry

Classifications

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G11C16/06

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title

• G06F2212/7207

  management of metadata or control data · CPC title