Transient current-protected threshold switching devices systems and methods

Patent metadata

Field	Value
Publication number	US-9852789-B2
Application number	US-201615333096-A
Country	US
Kind code	B2
Filing date	Oct 24, 2016
Priority date	Dec 26, 2015
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

Threshold switching devices demonstrating transient current protection through both insulation and repair current mechanisms, including associated systems and methods, are provided and discussed.

First claim

What is claimed is:

1. A computing system, comprising:
a memory array, further comprising:
a plurality of phase change memory (PCM) cells arranged in an array;
a plurality of word lines (WLs) coupled to groups of PCM cells across the array; and
a plurality of bit lines (BLs) coupled to groups of PCM cells across the array, such that each PCM cell is addressed in the array by a unique combination of a WL and a BL; and

circuitry electrically coupled to each WL and to each BL, the circuitry configured to:
generate memory control commands;
address the PCM cells in the array; and
read a state of each PCM cell in the array by:
selecting a PCM cell to be read having a selected BL (BLS) a selected WL (WLS) that uniquely addresses the selected PCM cell;
applying a WL read bias voltage (WLV) to the WLS;
uncoupling the WLS from the WLV to float the WLS;
applying a BL read bias voltage (BLV) to the BLS, such that the BLV and the WLV at the floating WLS activate the PCM cell; and
recoupling the WLS to the WLV to deliver a repair current to the PCM cell.

2. The system of claim 1 , further comprising a memory controller coupled to the plurality of WLs and the plurality of BLs to address the plurality of PCM cells in the array.

3. The system of claim 2 , wherein the circuitry comprises:
a WL select switch coupled between the WLV and the WLS, the WL select switch operable to gate coupling of the WLV to the WLS; and
a control input coupled to the WL select switch to operate the WL select switch.

4. The system of claim 3 , wherein the WL select switch comprises an NMOS transistor.

5. The system of claim 3 , wherein the BLS is to activate the WL select switch to couple the WLV to the WLS in response to application of the BLV to the BLS.

6. The system of claim 5 , wherein the circuitry comprises a bypass switch gated by the BLV, wherein activation of the bypass switch delivers the WLV from the floating WLS to gate the WL select switch, thereby coupling the WLV to the WLS.

7. The system of claim 6 , wherein the bypass switch comprises an NMOS transistor.

8. The system of claim 2 , wherein the circuitry further comprises a WLS device select switch coupled to the WLS between the WL select switch and a power source, wherein the WLS device select switch is gated by application of the WLV to the WLS device select switch.

9. The system of claim 8 , wherein the WLS device select switch comprises a PMOS transistor.

10. The system of claim 2 , wherein the circuitry further comprises a BLS device select switch coupled to the BLS between the BLS and a power source, wherein the BLS device select switch is gated by application of the BLV to the BLS device select switch.

11. The system of claim 10 , wherein the BLS device select switch comprises an NMOS transistor.

12. The system of claim 1 , wherein the circuitry further comprises I/O circuitry configured to control I/O operations of the system.

13. The system of claim 12 , wherein the I/O circuitry is configured to communicate with a processor.

14. The system of claim 1 , wherein the circuitry further comprises:
row circuitry coupled to the WLs; and
column circuitry coupled to the BLs, the column circuitry and the row circuitry being configured to address the plurality of PCM cells in the array.

15. The system of claim 14 , wherein the circuitry further comprises read/write circuitry coupled to the row circuitry and the column circuitry and configured to control read and write commands to and from plurality of PCM cells of the array.

16. The system of claim 2 , further comprising one or more of:
at least one processor communicatively coupled to the system;
a display communicatively coupled to the system;
a battery coupled to the system; or
a network interface communicatively coupled to the system.

17. A switching device, comprising:
a phase change material;
a word line (WL);
a bit line (BL) coupled to the WL across the phase change material; and
circuitry configured to:
activate the device by floating the WL and applying a BL read bias voltage (BLV); and
deliver a repair current by recoupling the WL to a WL read bias voltage (WLV).

18. The device of claim 17 , wherein the circuitry comprises:
a WL select switch coupled between the WLV and the WL, the WL select switch operable to gate coupling of the WLV to the WL; and
a control input coupled to the WL select switch to operate the WL select switch.

19. The device of claim 17 , further comprising a phase change memory material coupled between the WL and the BL adjacent to the phase change material.

20. The device of claim 17 , further comprising:
a plurality of phase change material elements arranged in an array;
a plurality of WLs coupled to groups of phase change material elements across the array;
a plurality of BLs coupled to groups of phase change memory elements across the array, such that each phase change memory element is addressed in the array by a unique combination of a WL and a BL; and
a controller coupled to the plurality of WLs and the plurality of BLs to address the plurality of phase change material elements in the array.

21. The device of claim 1 , wherein the switching device comprises an ovonic threshold switch.

22. The device of claim 1 , wherein the switching device comprises a phase change memory device.

Assignees

• Intel Corp

Inventors

• Mantegazza Davide
• Guliani Sandeep
• Srinivasan Balaji
• Pangal Kiran

Classifications

• G11C13/0023

  Address circuits or decoders · CPC title

• G11C13/0004 Primary

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C13/0026

  Bit-line or column circuits · CPC title

• G11C13/0028

  Word-line or row circuits · CPC title

• G11C29/70

  Masking faults in memories by using spares or by reconfiguring · CPC title