Semiconductor devices

Patent metadata

Field	Value
Publication number	US-11410997-B2
Application number	US-202016855321-A
Country	US
Kind code	B2
Filing date	Apr 22, 2020
Priority date	Sep 11, 2019
Publication date	Aug 9, 2022
Grant date	Aug 9, 2022

Abstract

A semiconductor device may include a substrate including first regions and a second region between the first regions. Active fins may protrude from the substrate in the first regions. Each of the active fins may extend in a first direction parallel to an upper surface of the substrate. The active fins may be regularly arranged and spaced apart from each other in a second direction. First trenches may be at both edges of the second region. A protrusion may be between the first trenches. An upper surface of the protrusion may be lower than a bottom of the active fins. A first width in the second direction of one of the first trenches may be greater than 0.7 times a first pitch of the active fins that is a sum of a width of one of the active fins and a distance between adjacent ones of the active fins.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate comprising first regions and a second region between the first regions;
active fins contiguous with and protruding from the substrate in the first regions, each of the active fins extending in a first direction that is parallel to an upper surface of the substrate, the active fins being regularly arranged and being spaced apart from each other in a second direction that is parallel to the upper surface of the substrate and perpendicular to the first direction;
first trenches at both edges in the second direction of the second region; and
a protrusion between the first trenches,
wherein an upper surface of the protrusion is substantially flat and lower than a bottom of each of the active fins, and
wherein a first width in the second direction of one of the first trenches is greater than 0.7 times a first pitch of the active fins that is a sum of a width of one of the active fins and a distance between adjacent ones of the active fins.

2. The semiconductor device of claim 1 , wherein a first active fin of the active fins is at an edge portion among the active fins in the second direction, and an end portion of the first active fin extending laterally from a lower portion of the first active fin is connected to a sidewall of the one of the first trenches, and the end portion of the first active fin and the sidewall of the one of the first trenches have a non-linear shape.

3. The semiconductor device of claim 1 , wherein a sidewall slope, which is an angle between a sidewall of the one of the first trenches and a line parallel to a bottom of the one of the first trenches, is in a range of 85° to 90°.

4. The semiconductor device of claim 1 , wherein a second width in the second direction of the protrusion is greater than 0.7 times the first pitch.

5. The semiconductor device of claim 1 , wherein a sidewall slope, which is an angle between a sidewall of the protrusion and a line parallel to a bottom of the one of the first trenches, is in a range of 80° to 90°.

6. The semiconductor device of claim 1 , wherein each of the active fins comprises a lower active fin and an upper active fin on the lower active fin, and wherein a first isolation pattern is in a gap between adjacent ones of the lower active fins.

7. The semiconductor device of claim 6 , further comprising an isolation structure comprising a second isolation pattern in the one of the first trenches and a third isolation pattern on the protrusion, wherein an upper surface of the isolation structure is coplanar with an upper surface of the first isolation pattern.

8. The semiconductor device of claim 7 , further comprising:
a gate structure extending in the second direction on the active fins, the first isolation pattern, and the isolation structure; and
a source/drain layer on the active fins adjacent to the gate structure.

9. The semiconductor device of claim 1 , wherein a second height from a top surface of the one of the active fins to a bottom of the one of the first trenches is greater than 130% of a first height from the top surface of the one of the active fins to the bottom of the one of the active fins.

10. The semiconductor device of claim 1 , wherein the protrusion is one of a plurality of protrusions in the substrate of the second region, and a second trench is between adjacent ones of the protrusions.

11. The semiconductor device of claim 10 , wherein a second width in the second direction of the second trench is greater than 0.7 times the first pitch.

12. The semiconductor device of claim 1 , wherein the first width of the one of the first trenches is less than 20 times the first pitch.

13. The semiconductor device of claim 1 , wherein the first width of the one of the first trenches is in a range of 10 nm to 500 nm.

14. The semiconductor device of claim 1 , wherein a bottom surface of the one of the first trenches is lower than the upper surface of the protrusion.

15. A semiconductor device, comprising:
a substrate comprising first regions and a second region between the first regions;
active fins contiguous with and protruding from the substrate in the first regions, each of the active fins extending in a first direction that is parallel to an upper surface of the substrate, the active fins being regularly arranged and being spaced apart from each other in a second direction that is parallel to the upper surface of the substrate and perpendicular to the first direction, wherein each of the active fins comprises a lower active fin and an upper active fin on the lower active fin;
first trenches at both edges in the second direction of the second region;
a protrusion between the first trenches having an upper surface that is substantially flat;
a first isolation pattern in a gap between the lower active fins;
an isolation structure comprising a second isolation pattern in at least one of the first trenches and a third isolation pattern on the protrusion; and
a gate structure extending in the second direction on the active fins, the first isolation pattern, and the isolation structure,
wherein an upper surface of the protrusion and a bottom of the at least one of the first trenches are lower than a bottom of one of the active fins.

16. The semiconductor device of claim 15 , wherein a first width in the second direction of the at least one of the first trenches is greater than 0.7 times a first pitch of the active fins that is a sum of a width of one of the active fins and a distance between adjacent ones of the active fins.

17. A semiconductor device, comprising:
a substrate comprising first regions and a second region between the first regions;
active fins contiguous with and protruding from the substrate in the first regions, each of the active fins extending in a first direction that is parallel to an upper surface of the substrate, the active fins being regularly arranged and being spaced apart from each other in a second direction that is parallel to the upper surface of the substrate and perpendicular to the first direction;
first trenches being at both edges in the second direction of the second region; and
protrusions being between the first trenches and having substantially flat upper surfaces,
wherein a first active fin of the active fins is at an edge portion among the active fins in the second direction, and an end portion of the first active fin extending laterally from a lower portion of the first active fin is connected to a sidewall of one of the first trenches, and the end portion of the first active fin and the sidewall of the one of the first trenches have a non-linear shape.

18. The semiconductor device of claim 17 , wherein a first width of the one of the first trenches in the second direction is greater than 0.7 times a first pitch of the active fins that is a sum of a width of one of the active fins and a distance between adjacent ones of the active fins.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Junghan
• Kwon Taeyong
• Sun Minchul
• Kim Byounggi
• Park Suhyeon
• Lee Kihwan

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title