Semiconductor structure

Patent metadata

Field	Value
Publication number	US-9837282-B1
Application number	US-201715667641-A
Country	US
Kind code	B1
Filing date	Aug 3, 2017
Priority date	Dec 1, 2016
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

A semiconductor structure includes a semiconductor substrate with a first region and a second region defined thereon. The first region is disposed adjoining the second region in a first direction. The semiconductor substrate includes fin structures, first recessed fins, and a bump. The fin structures are disposed in the first region. Each fin structure is elongated in the first direction. The first recessed fins are disposed in the second region. Each first recessed fin is elongated in the first direction. A topmost surface of each first recessed fin is lower than a topmost surface of each fin structure. The bump is disposed in the second region and disposed between two adjacent recessed fins in the first direction. A topmost surface of the bump is higher than the topmost surface of each first recessed fin and lower than the topmost surface of each fin structure.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a semiconductor substrate with a first region and a second region defined thereon, wherein the first region is disposed adjoining the second region in a first direction, and the semiconductor substrate comprises:
a plurality of fin structures disposed in the first region, wherein each of the fin structures is elongated in the first direction;
a plurality of first recessed fins disposed in the second region, wherein each of the first recessed fins is elongated in the first direction, and a topmost surface of each of the first recessed fins is lower than a topmost surface of each of the fin structures; and
a bump disposed in the second region, wherein the bump is disposed between two adjacent first recessed fins in the first direction, and a topmost surface of the bump is higher than the topmost surface of each of the first recessed fins and lower than the topmost surface of each of the fin structures.

2. The semiconductor structure according to claim 1 , wherein at least a part of the fin structures are repeatedly disposed in a second direction different from the first direction, and a top surface of a part of the semiconductor substrate disposed between two adjacent fin structures in the second direction is lower than the topmost surface of each of the first recessed fins.

3. The semiconductor structure according to claim 1 , wherein the second direction is orthogonal to the first direction.

4. The semiconductor structure according to claim 1 , wherein the semiconductor substrate further comprises:
a second recessed fin disposed in the first region and disposed between two adjacent fin structures in the first direction, wherein a topmost surface of the second recessed fin is lower than the topmost surface of each of the fin structures.

5. The semiconductor structure according to claim 4 , wherein the topmost surface of the second recessed fin is higher than the topmost surface of each of the first recessed fins.

6. The semiconductor structure according to claim 4 , wherein the topmost surface of the second recessed fin and the topmost surface of the bump are located at the same level.

7. The semiconductor structure according to claim 4 , wherein the second recessed fin is directly connected with the two adjacent fin structures in the first direction.

8. The semiconductor structure according to claim 1 , wherein the bump is directly connected with the two adjacent first recessed fins in the first direction.

9. The semiconductor structure according to claim 1 , wherein at least one of the first recessed fins is disposed between the bump and one of the fin structures in the first direction.

10. The semiconductor structure according to claim 9 , wherein the first recessed fin disposed between the bump and the fin structure in the first direction is directly connected with the bump and the fin structure in the first direction.

11. The semiconductor structure according to claim 1 , further comprising:
a shallow trench isolation disposed on the semiconductor substrate, wherein the topmost surface of each of the first recessed fins and the topmost surface of the bump are covered by the shallow trench isolation, and the fin structures protrude above a topmost surface of the shallow trench isolation.

12. The semiconductor structure according to claim 11 , wherein the topmost surface of the shallow trench isolation is lower than the topmost surface of each of the fin structures.

Assignees

• United Microelectronics Corp

Inventors

• Weng Tang-Chun
• Lin Chia-Ching
• Chen Yen-Pu
• Liou En-Chiuan

Classifications

• H10P50/693

  characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10P74/203 Primary

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H01L29/66545

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic