Fin-type field effect transistor structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9899526-B2
Application number	US-201614996236-A
Country	US
Kind code	B2
Filing date	Jan 15, 2016
Priority date	Jan 15, 2016
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

A fin-type field effect transistor comprising a substrate, fins, insulators, at least one gate stack and strained material portions is described. The insulators are disposed in trenches of the substrate and between the fins. The upper portion of the fin is higher than a top surface of the insulator and the upper portion has a substantially vertical profile, while the lower portion of the fin is lower than the top surface of the insulator and the lower portion has a tapered profile. The at least one gate stack is disposed over the fins and on the insulators. The strained material portions are disposed on two opposite sides of the at least one gate stack.

First claim

What is claimed is:

1. A fin-type field effect transistor, comprising:
a substrate having trenches and fins between the trenches, wherein the fin comprises an upper portion and a lower portion;
at least one first dummy fin located further away from the fins and at least one second dummy fin located nearer to the fins, wherein a height of the at least one second dummy fin is about 1.5 times to 4 times of a height of the at least one first dummy fin, and a height of the fins is about 20 times of the height of the at least one first dummy fin;
insulators, disposed in the trenches of the substrate and between the fins, wherein the upper portion of the fin is higher than a top surface of the insulator and the upper portion has a substantially vertical profile, while the lower portion of the fin is lower than the top surface of the insulator and the lower portion has a tapered profile, and the substantially vertical profile of the upper portion changes into the tapered profile of the lower portion with a slope change once;
at least one gate stack, disposed over the fins and on the insulators; and
strained material portions, disposed on two opposite sides of the at least one gate stack.

2. The transistor of claim 1 , wherein a fin width of the upper portion at a top point is substantially equivalent to a fin width of the fin at a separating point of the upper and lower portions, and a fin width of the lower portion at a bottom point is larger than the fin width of the fin at the separating point of the upper and lower portions.

3. The transistor of claim 1 , wherein a fin width of the upper portion at a top point is substantially equivalent to a fin width of the fin at a separating point of the upper and lower portions, and a fin width of the lower portion at a bottom point is about two times of the fin width of the fin at the separating point of the upper and lower portions.

4. The transistor of claim 1 , wherein a spacing between the fins is substantially equal.

5. The transistor of claim 1 , wherein a material of the strained material portions comprise silicon germanium (SiGe), silicon carbon (SiC) or silicon phosphide (SiP).

6. The transistor of claim 1 , wherein the at least one gate stack comprises:
a gate dielectric layer covering portions of the fins and disposed on the insulators;
a gate electrode layer disposed on the gate dielectric layer; and
spacers disposed on sidewalls of the gate dielectric layer and the gate electrode layer.

7. A fin-type field effect transistor, comprising:
a substrate having trenches and fins between the trenches;
insulators, disposed in the trenches of the substrate and between the fins, wherein lower portions of the fins lower than the top surfaces of the insulators are sandwiched between the insulators and the lower portions have tapered profiles;
at least one first dummy fin located further away from the fins and at least one second dummy fin located nearer to the fins, wherein a height of the at least one second dummy fin is about 1.5 times to 4 times of a height of the at least one first dummy fin, and a height of the fins is about 20 times of the height of the at least one first dummy fin;
at least one gate stack, disposed over the fins and on the insulators, wherein upper portions of the fins higher than the top surfaces of the insulators are covered by the at least one gate stack, and the upper portions have substantially vertical profiles, and the substantially vertical profile of the upper portion changes into the tapered profile of the lower portion with a slope change once; and
strained material portions, disposed on two opposite sides of the at least one gate stack.

8. The transistor of claim 7 , wherein a fin width of the upper portion at a top point is substantially equivalent to a fin width of the fin at a separating point of the upper and lower portions, and a fin width of the lower portion at a bottom point is about two times of the fin width of the fin at the separating point of the upper and lower portions.

9. The transistor of claim 7 , wherein a spacing between the fins is substantially equal.

10. A fin-type field effect transistor, comprising:
a substrate having trenches and fins, dummy fins and additional dummy fins located between the trenches, wherein the dummy fins are located at outer sides of the fins, a height of the fins is about 5 times to 13.3 times of a height of the dummy fins, the additional dummy fins are located further away from the dummy fins and the additional dummy fins are shorter than the dummy fins, and the fin comprises an upper portion having a substantially vertical profile and a lower portion having a tapered profile, and wherein the substantially vertical profile of the upper portion changes into the tapered profile of the lower portion with a slope change once;
insulators, disposed in the trenches and between the fins and covering the dummy fins, wherein the upper portion of the fin is higher than a top surface of the insulator and the lower portion of the fin is lower than the top surface of the insulator;
at least one gate stack, disposed over the fins and on the insulators; and
strained material portions, disposed on two opposite sides of the at least one gate stack.

11. The transistor of claim 10 , wherein a fin width of the upper portion at a top point is substantially equivalent to a fin width of the fin at a separating point of the upper and lower portions, and a fin width of the lower portion at a bottom point is larger than the fin width of the fin at the separating point of the upper and lower portions.

12. The transistor of claim 10 , wherein a fin width of the upper portion at a top point is substantially equivalent to a fin width of the fin at a separating point of the upper and lower portions, and a fin width of the lower portion at a bottom point is about two times of the fin width of the fin at the separating point of the upper and lower portions.

13. The transistor of claim 10 , wherein the fins are uniform with a substantially equal critical dimension and a substantially equal spacing between the fins.

14. The transistor of claim 10 , wherein a height of the fins is about 20 times of a height of the additional dummy fins.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chiu Yi Wei
• Hsu Li Te
• Huang Chung Fan
• Chu Chih Hsiang

Classifications

• H01L29/7853 Primary

  Electricity · mapped topic

• H01L29/7848

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title