Tungsten feature fill with nucleation inhibition

Patent metadata

Field	Value
Publication number	US-11410883-B2
Application number	US-201916294736-A
Country	US
Kind code	B2
Filing date	Mar 6, 2019
Priority date	Aug 4, 2009
Publication date	Aug 9, 2022
Grant date	Aug 9, 2022

Abstract

Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. In certain embodiments, the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration using through-silicon vias.

First claim

The invention claimed is:

1. A method comprising:
providing a substrate having a surface and including a structure having one or more horizontally-oriented features, each horizontally-oriented feature having a longest dimension that is oriented horizontally with respect to the substrate surface; to be filled with a tungsten-containing material, the one or more horizontally-oriented features having feature openings and interior regions accessible through the feature openings; and
inhibiting tungsten nucleation in the one or more horizontally-oriented features such that tungsten nucleation is inhibited more at the feature openings than at the interior regions.

2. The method of claim 1 , further comprising depositing the tungsten-containing material in the one or more horizontally-oriented features.

3. The method of claim 1 , wherein the structure comprises a partially fabricated three-dimensional (3-D) NAND structure and the one or more horizontally-oriented features comprises tungsten wordline features.

4. The method of claim 1 , wherein inhibiting tungsten nucleation in the one or more horizontally-oriented features comprises exposing the structure to a direct plasma.

5. The method of claim 1 , wherein inhibiting tungsten nucleation in the one or more horizontally-oriented features comprises exposing the structure to a remotely-generated plasma.

6. The method of claim 1 , wherein inhibiting tungsten nucleation in the one or more horizontally-oriented features comprises exposing the structure to a plasma while applying a bias voltage to the substrate.

7. The method of claim 1 , wherein inhibiting tungsten in the one or more horizontally-oriented features comprises exposing the structure to one or more of activated species of nitrogen, hydrogen, oxygen, or carbon.

8. The method of claim 1 , further comprising depositing a tungsten-containing layer in the one or more horizontally-oriented features prior to inhibition.

9. The method of claim 1 , wherein inhibiting tungsten nucleation comprises treating a tungsten-containing surface of the one or more horizontally-oriented features.

10. The method of claim 1 , wherein inhibiting tungsten nucleation comprises treating a metal nitride surface of the one or more horizontally-oriented features.

11. The method of claim 1 , wherein inhibiting tungsten nucleation in the one or more horizontally-oriented features comprises passivating a feature surface without forming a compound material.

12. The method of claim 1 , wherein selectively inhibiting tungsten nucleation in the one or more horizontally-oriented features comprises forming a tungsten compound material.

13. The method of claim 1 , wherein inhibiting tungsten nucleation comprises exposing the one or more horizontally-oriented features to nitrogen species.

14. The method of claim 1 , wherein inhibiting tungsten nucleation comprises exposing the one or more horizontally oriented features to hydrogen species.

15. A method comprising:
providing a substrate including a feature having one or more feature openings and a feature interior, the feature interior defined at least in part by a feature sidewall extending from a feature opening; and
exposing the feature to a non-ionic remotely-generated plasma to selectively inhibit tungsten nucleation in the interior of the feature such that there is a differential inhibition profile along a feature axis such that the feature sidewall is more inhibited near the feature opening than deeper into the feature interior.

16. The method of claim 15 , further comprising selectively depositing tungsten in the feature in accordance with the differential inhibition profile.

17. The method of claim 15 , wherein the feature is a horizontally-oriented feature having at least openings and the feature axis is horizontally-oriented.

18. The method of claim 17 , wherein the feature is a wordline feature in a 3-D NAND structure.

19. The method of claim 15 , wherein the feature is provided with a tungsten layer lining the feature and the exposing the feature to a non-ionic remotely-generated plasma to selectively inhibit tungsten nucleation comprises exposing the tungsten layer to the non-ionic remotely generated plasma.

Assignees

• Novellus Systems Inc

Inventors

• Chandrashekar Anand
• Jeng Esther
• Humayun Raashina
• Danek Michal
• Gao Juwen
• Wang Deqi

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/0261

  characterised by the filling method or the material of the conductive fill · CPC title

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P14/43

  Chemical deposition, e.g. chemical vapour deposition [CVD] · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title