Fan out package with integrated peripheral devices and methods

Patent metadata

Field	Value
Publication number	US-11404339-B2
Application number	US-202016894434-A
Country	US
Kind code	B2
Filing date	Jun 5, 2020
Priority date	Mar 28, 2018
Publication date	Aug 2, 2022
Grant date	Aug 2, 2022

Abstract

A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a processor die, including a plurality of die contacts extending above a top surface of the die;
an integrated routing layer directly deposited on the plurality of die contacts, wherein the integrated routing layer includes a routing layer width that is wider than the die;
one or more solder bumps coupled directly to the integrated routing layer such that the integrated routing layer is between the die and the one or more solder bumps;
a single encapsulant covering one or more sides of the die, and surrounding the plurality of die contacts, the single encapsulant extending laterally to the same width as the integrated routing layer;
at least one encapsulated peripheral component located laterally adjacent to the processor die, and coupled directly to the integrated routing layer, wherein the at least one encapsulated peripheral component is a passive component, wherein a back surface of the die is a top surface of the semiconductor device.

2. The semiconductor device of claim 1 , wherein the at least one encapsulated peripheral component includes a capacitor.

3. The semiconductor device of claim 1 , wherein the at least one encapsulated peripheral component includes an inductor.

4. The semiconductor device of claim 1 , wherein the at least one encapsulated peripheral component is formed within a silicon substrate.

5. The semiconductor device of claim 1 , wherein the plurality of die contacts include a plurality of copper bumps.

6. The semiconductor device of claim 1 , wherein the at least one encapsulated peripheral component includes multiple peripheral components of different passive component types.

7. A semiconductor device, comprising:
a processor die, including a plurality of die contacts;
an integrated routing layer directly deposited on the plurality of die contacts, wherein the integrated routing layer includes a routing layer width that is wider than the die;
one or more solder bumps coupled directly to the integrated routing layer such that the integrated routing layer is between the die and the one or more solder bumps;
a single encapsulant covering one or more sides of the die, and surrounding the plurality of die contacts, the single encapsulant extending laterally to the same width as the integrated routing layer; and
at least one encapsulated peripheral component located laterally adjacent to the processor die, and coupled directly to the integrated routing layer, wherein the at least one encapsulated peripheral component is a passive component, wherein a back surface of the die is a top surface of the semiconductor device.

8. The semiconductor device of claim 7 , wherein the at least one encapsulated peripheral component includes a capacitor.

9. The semiconductor device of claim 7 , wherein the at least one encapsulated peripheral component includes an inductor.

10. The semiconductor device of claim 7 , wherein the at least one encapsulated peripheral component is formed within a silicon substrate.

11. The semiconductor device of claim 7 , wherein the plurality of die contacts include a plurality of copper bumps.

12. The semiconductor device of claim 7 , wherein the at least one encapsulated peripheral component includes multiple peripheral components of different passive component types.

13. The semiconductor device of claim 7 , wherein the single encapsulant includes a planar surface that is coplanar with the plurality of die contacts.

14. A semiconductor device, comprising:
a processor die, including a plurality of die contacts;
an integrated routing layer deposited on the plurality of die contacts without solder, wherein the integrated routing layer includes a routing layer width that is wider than the die;
a single encapsulant covering one or more sides of the die, and surrounding the plurality of die contacts, the single encapsulant extending laterally to the same width as the integrated routing layer; and
at least one encapsulated peripheral component located laterally adjacent to the processor die, and coupled directly to the integrated routing layer, wherein the at least one encapsulated peripheral component is a passive component, wherein a back surface of the die is a top surface of the semiconductor device.

15. The semiconductor device of claim 14 , further including one or more solder bumps coupled directly to the integrated routing layer such that the integrated routing layer is between the die and the one or more solder bumps.

16. The semiconductor device of claim 14 , wherein the at least one encapsulated peripheral component includes a capacitor.

17. The semiconductor device of claim 14 , wherein the at least one encapsulated peripheral component includes an inductor.

18. The semiconductor device of claim 14 , wherein the at least one encapsulated peripheral component is formed within a silicon substrate.

Assignees

• Intel Ip Corp
• Intel Corp

Inventors

• Keser Lizabeth
• Waidhas Bernd
• Ort Thomas
• Wagner Thomas

Classifications

• H10W70/655

  Fan-out layouts · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/20 Primary

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/012

  of bump connectors, dummy bumps or thermal bumps · CPC title