Semiconductor package and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-9922845-B1
Application number	US-201615342124-A
Country	US
Kind code	B1
Filing date	Nov 3, 2016
Priority date	Nov 3, 2016
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

A method for fabricating a semiconductor package is disclosed. A substrate is provided and a first passivation layer is formed on the substrate. Trenches are formed partially through the substrate. Metal via structures are formed in the trenches. An RDL structure is formed on the first passivation layer. A second passivation layer is formed on the RDL structure. Openings are formed in the second passivation layer to expose bump pads. First metal pillars are formed on the bump pads. Semiconductor dies are mounted onto the metal pillars. A molding compound is formed to cover the semiconductor dies. The substrate is removed, thereby exposing the first passivation layer and protrudent portions (second metal pillars) of the metal via structures. C4 bumps are formed directly on the second metal pillars, respectively.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device package, the method comprising:
providing a substrate having opposite first and second surfaces;
forming metal via structures extending into the first surface of the substrate, comprising:
forming a first passivation layer on the first surface of the substrate;
forming a plurality of trenches penetrating through the first passivation layer and partially through the substrate; and
filling the plurality of trenches with a conductive material;

forming a redistribution layer (RDL) structure on the substrate to electrically connect the metal via structures;
forming first metal pillars on the RDL structure;
performing a die attachment process to mount semiconductor dies onto the first metal pillars;
removing the substrate to expose protrudent portions of the metal via structures to form second metal pillars, comprising:
subjecting the substrate to a substrate thinning process to remove a portion of the substrate; and
performing a wet etch back process to remove a remaining portion of the substrate to expose the first passivation layer and the protrudent portion of each of the metal via structures; and

forming connecting elements on the second metal pillars.

2. The method of claim 1 , further comprising forming each of the trenches to a depth that is not greater than 50 micrometers.

3. The method of claim 1 , further comprising forming the trenches to substantially the same diameter.

4. The method of claim 1 , further comprising forming the trenches to different diameters.

5. The method of claim 1 , wherein filling the trenches with a conductive material comprises filing the trenches with copper, chrome, nickel, aluminum, gold, silver, tungsten, titanium, or titanium nitride.

6. The method of claim 1 , wherein filling the trenches with a conductive material comprises forming a multiple layer structure in the trenches comprising an adhesive layer, a barrier metals, a seed layer, a wetting layer, or combinations thereof.

7. The method of claim 1 , wherein forming first metal pillars on the RDL structure comprises:
forming a second passivation layer on the RDL structure;
forming pad openings in the second passivation layer to expose bump pads of the RDL structure; and
forming the first metal pillars on the bump pads, respectively.

8. The method of claim 7 , wherein forming the first passivation layer and the second passivation layer comprise forming from silicon nitride, silicon oxide, silicon oxy-nitride, polyimide, or a combination thereof.

9. The method of claim 1 , wherein providing a substrate comprises providing a silicon substrate.

10. The method of claim 1 , further comprising:
forming a molding compound to cover the semiconductor dies and the first passivation layer; and
polishing the molding compound to expose passive surfaces of the semiconductor dies and a surface of the molding compound is coplanar with the passive surfaces.

11. The method of claim 1 , wherein the first metal pillars are formed as micro-bumps and the second metal pillars are formed as under bump metallurgy (UBM) bumps.

12. The method of claim 11 , wherein forming the first metal pillars comprises forming a UBM structure and forming a conductive bump capping the UBM structure.

13. The method of claim 12 , wherein forming the conductive bump comprises forming a solder bump or a metal bump.

14. The method of claim 1 , wherein forming the connecting elements comprises forming solder bumps or C4 bumps.

15. A method for fabricating a semiconductor package, comprising:
providing a substrate having opposite first and second surfaces;
forming metal via structures extending into the first surface of the substrate;
forming a redistribution layer (RDL) structure on the substrate to electrically connect the metal via structures;
forming first metal pillars on the RDL structure;
attaching a carrier to the RDL structure;
removing the substrate to expose protrudent portions of the metal via structures to form second metal pillars;
mounting semiconductor dies on the second metal pillars;
removing the carrier to expose the first metal pillars and the second passivation layer; and
forming connecting elements directly on the first metal pillars.

16. The method of claim 15 , wherein removing the substrate to expose a protrudent portion of each of the metal via structures comprises:
subjecting the substrate to a substrate thinning process to remove a portion of the substrate; and
performing a wet etch back process to remove a remaining portion of the substrate, to expose the first passivation layer and the protrudent portions of the metal via structures.

17. The method of claim 16 , further comprising:
forming a molding compound to cover the semiconductor dies and the first passivation layer; and
polishing the molding compound to expose passive surfaces of the semiconductor dies are exposed and a surface of the molding compound is coplanar with the passive surfaces.

18. The method of claim 15 , wherein the first metal pillars are formed as UBM bumps and the second metal pillars are formed as micro-bumps.

Assignees

• Micron Technology Inc

Inventors

• Shih Shing-Yih

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W90/00

  Package configurations · CPC title