Passive Devices in Package-on-Package Structures and Methods for Forming the Same

Patent metadata

Field	Value
Publication number	US-2016233161-A1
Application number	US-201615133326-A
Country	US
Kind code	A1
Filing date	Apr 20, 2016
Priority date	Sep 20, 2012
Publication date	Aug 11, 2016
Grant date	—

Abstract

A device includes a polymer. A device die is disposed in the polymer. A passive device includes three Through Assembly Vias (TAVs) penetrating through the polymer, wherein the TAVs are coupled in series. A Redistribution Line (RDL) is underlying the polymer. The RDL electrically couples a first one of the TAVs to a second one of the TAVs.

First claim

What is claimed is:

1 . A method comprising:
placing a device die over a carrier; forming a plurality of through-vias over the carrier; encapsulating the device die and the plurality of through-vias in a encapsulating material; thinning the encapsulating material, wherein after the thinning, ends of the through-vias are level with ends of conductive pillars of the device die, and wherein the ends of the through-vias and the ends of the conductive pillars are exposed through the encapsulating material; forming a first plurality of Redistribution Lines (RDLs) on a first side of the encapsulating material, wherein the first plurality of RDLs is electrically coupled to the plurality of through-vias; and interconnecting the plurality of through-vias using a plurality of conductive features to form a passive device, wherein the plurality of conductive features and the first plurality of RDLs are on opposite sides of the encapsulating material, and wherein the passive device comprises the plurality of through-vias and one of the first plurality of RDLs.

2 . The method of claim 1 , wherein the interconnecting the plurality of through-vias comprises forming a second plurality of RDLs as the plurality of conductive features.

3 . The method of claim 1 , wherein the interconnecting the plurality of through-vias comprises bonding a package component to the plurality of through-vias, wherein a conductive line in the package component forms a part of the passive device, and wherein the conductive line in the package component and the plurality of through-vias are coupled in series.

4 . The method of claim 3 , wherein the bonding is performed using a plurality of solder region, wherein the plurality of solder regions and the plurality of through-vias are coupled in series, and wherein the plurality of solder regions form parts of the passive device.

5 . The method of claim 1 , wherein the passive device comprises a coil, wherein the method further comprises forming a paramagnetic line parallel to an axis of the coil and inside the coil, and wherein the paramagnetic line is formed simultaneously when one of the first plurality of RDLs is formed.

6 . The method of claim 1 , wherein the plurality of through-vias is electrically coupled in series with each other, and the plurality of through-vias is serially and electrically coupled to the plurality of conductive features.

7 . The method of claim 1 , wherein the plurality of through-vias, the plurality of conductive features, and the first plurality of RDLs are all connected in series to form the passive device.

8 . The method of claim 1 , wherein the encapsulating material comprises a molding compound.

9 . A method comprising:
encapsulating a plurality of through-vias in an encapsulating material; performing a planarization to level ends of the plurality of through-vias with a surface of the encapsulating material; forming a first plurality of conductive lines on a first side of the encapsulating material; and forming a second plurality of conductive lines on a second side of the encapsulating material, wherein the plurality of through-vias, the first plurality of conductive lines, and the second plurality of conductive lines are electrically coupled in series to form a coil.

10 . The method of claim 9 further comprising forming a plurality of solder regions, each aligned to one of the plurality of through-vias, wherein the plurality of solder regions is serially coupled with each other to form parts of the coil.

11 . The method of claim 10 further comprising bonding a package component to the plurality of through-vias through the plurality of solder regions, wherein the package component comprises a plurality of conductive lines therein, with the plurality of conductive lines coupled in series to inter-couple the plurality of through-vias.

12 . The method of claim 9 further comprising, when the plurality of through-vias is encapsulated, simultaneously encapsulating a device die in the encapsulating material.

13 . The method of claim 9 , wherein the encapsulating the plurality of through-vias in the encapsulating material comprises disposing a molding compound.

14 . The method of claim 9 further comprising:
pre-forming the plurality of through-vias before the encapsulating.

15 . The method of claim 9 further comprises forming a paramagnetic line parallel to an axis of the coil and inside the coil, wherein the paramagnetic line is formed simultaneously when one of the first plurality of RDLs is formed.

16 . A method comprising:
forming a plurality of through-vias over a carrier; encapsulating the plurality of through-vias in an encapsulating material; planarizing the encapsulating material, wherein after the planarizing, ends of the plurality of through-vias are substantially coplanar with a surface of the encapsulating material, and the ends of the plurality of through-vias are exposed through the encapsulating material; forming a first plurality of Redistribution Lines (RDLs) and a paramagnetic line simultaneously on a first side of the encapsulating material, wherein the first plurality of RDLs is electrically coupled to the plurality of through-vias; forming a second plurality of RDLs electrically coupled to the first plurality of RDLs; and forming a third plurality of RDLs on a second side of the encapsulating material opposite to the first side, wherein the first plurality of RDLs and the third plurality of RDLs are on opposite sides of the encapsulating material, and the first, the second, and the third plurality of RDLs and the plurality of through-vias are coupled serially to form a coil, with the paramagnetic line being encircled by the coil.

17 . The method of claim 16 further comprising forming a dielectric layer on the first side of the encapsulating material, with the first plurality of RDLs extending into the dielectric layer, wherein the paramagnetic line is in the dielectric layer.

18 . The method of claim 16 further comprising bonding a package component to the plurality of through-vias through a plurality of solder regions, wherein the package component comprises a plurality of conductive lines therein, with the plurality of conductive lines and the plurality of solder regions in combination inter-coupling the plurality of through-vias.

19 . The method of claim 16 , wherein the encapsulating the plurality of through-vias in the encapsulating material comprises disposing a molding compound.

20 . The method of claim 16 further comprising pre-forming the plurality of through-vias before the encapsulating, wherein the forming the plurality of through-vias comprises plating.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Chih-Hua
• Chen Chen-Shien

Classifications

• H10P72/74 Primary

  using temporarily an auxiliary support · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title