Method for manufacturing semiconductor device and system for performing the same

Patent metadata

Field	Value
Publication number	US-11392045-B2
Application number	US-202017114300-A
Country	US
Kind code	B2
Filing date	Dec 7, 2020
Priority date	Nov 15, 2017
Publication date	Jul 19, 2022
Grant date	Jul 19, 2022

Abstract

A method for manufacturing a structure on a substrate includes projecting an image of a reference pattern onto a substrate having a first patterned layer, the first patterned layer including first alignment marks and first overlay measurement marks, and the reference pattern including second alignment marks and second overlay measurement marks, aligning, based on the first alignment marks and the second alignment marks, the first patterned layer to the image of the reference pattern, obtaining a pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks, and determining compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.

First claim

What is claimed is:

1. A semiconductor manufacturing tool, comprising:
an alignment tool;
an overlay measurement tool;
a substrate stage on which a substrate having a patterned layer is disposed;
a processor; and
a non-transitory storage medium storing instructions, when executed, causing the processor to:
transmit a signal to the alignment tool to cause the alignment tool to project an image of a reference pattern on the substrate;
cause the alignment tool to perform alignment of the patterned layer to the projected image, based on first alignment marks in the patterned layer and second alignment marks provided by the projected image;
cause the overlay measurement tool to obtain pre-overlay mapping of first overlay measurement marks in the patterned layer and second overlay measurement marks provided by the projected image; and
determine compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.

2. The semiconductor manufacturing tool of claim 1 , wherein the non-transitory storage medium storing instructions, when executed, further causes the processor to:
transmit a signal indicating the compensation data to another semiconductor tool to cause the another semiconductor tool to adjust a parameter in response to the received signal.

3. The semiconductor manufacturing tool of claim 1 , further comprising an exposure tool,
wherein the non-transitory storage medium storing instructions, when executed, further causes the processor to:
adjust a parameter of the alignment tool;
after adjusting the parameter of the alignment tool, cause the alignment tool to re-perform alignment of the patterned layer to the projected image; and
after re-performing the alignment, cause the exposure tool to expose a photoresist layer coated on the patterned layer.

4. The semiconductor manufacturing tool of claim 3 , wherein the exposure tool further comprises:
an ultraviolet radiation source;
an illumination module; and
a projection module.

5. The semiconductor manufacturing tool of claim 1 , further comprising an image capturing device configured to capture an image of the first alignment marks in the patterned layer and the second alignment marks provided by the projected image.

6. The semiconductor manufacturing tool of claim 5 , wherein the processor is configured to determine a relative position or attitude associated with an overlay of the first alignment marks and the second alignment marks based on the image captured by the image capturing device.

7. The semiconductor manufacturing tool of claim 1 , further comprising a spot beam source configured to generate the image of the reference pattern.

8. The semiconductor manufacturing tool of claim 1 , further comprising a moving tool configured to adjust a position of the substrate stage.

9. The semiconductor manufacturing tool of claim 8 , wherein the moving tool is controlled by the alignment tool.

10. A semiconductor manufacturing system, comprising:
a virtual alignment and pre-overlay measurement tool configured to:
project an image of a reference pattern onto a substrate,
virtually align a first patterned layer to the projected image based on first alignment marks in the first patterned layer and second alignment marks provided by the projected image,
obtain a pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks, and
determine compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks;

an alignment and exposure tool configured to:
align a photomask to the first patterned layer based on the compensation data, and expose a photoresist layer coated on the first patterned layer; and
a developing tool configured to develop the exposed photoresist layer.

11. The semiconductor manufacturing system of claim 10 , wherein among the virtual alignment and pre-overlay measurement tool and the alignment and exposure tool, only the alignment and exposure tool comprises a radiation source for exposing the photoresist layer.

12. The semiconductor manufacturing system of claim 10 , further comprising a pattern database configured to store pattern data,
wherein the virtual alignment and pre-overlay measurement tool is configured to receive the pattern data from the pattern database.

13. The semiconductor manufacturing tool of claim 10 , further comprising an image capturing device configured to capture an image of the first alignment marks in the patterned layer and the second alignment marks provided by the projected image.

14. The semiconductor manufacturing tool of claim 13 , further comprising a processor,
wherein the processor is configured to determine a relative position or attitude associated with an overlay of the first alignment marks and the second alignment marks based on the image captured by the image capturing device.

15. The semiconductor manufacturing system of claim 10 , further comprising a spot beam source configured to generate the image of the reference pattern.

16. The semiconductor manufacturing tool of claim 10 , further comprising:
a substrate stage configured to support the substrate; and
a moving tool configured to adjust a position of the substrate stage.

17. A semiconductor manufacturing tool, comprising:
a projection tool comprising:
a light source configured to generate a virtual mask in response to information of pattern data received from a pattern database;
an illumination module; and
a projection module,
wherein the illumination module is configured to direct light from the light source onto the projection module, and the projection module is configured to direct light from the illumination module onto a substrate on a substrate stage;

a position adjustment tool configured to adjust a position of the substrate stage;
an alignment tool configured to control the position adjustment tool;
an image capturing device configured to capture an image of alignment marks on the substrate and alignment marks of the virtual mask projected onto the substrate; and
a controller controlling the projection tool and the image capturing device.

18. The semiconductor manufacturing tool of claim 17 , wherein the light source is a spot beam source.

19. The semiconductor manufacturing tool of claim 17 , further comprising an exposure tool configured to expose a photoresist layer coated on the substrate to ultraviolet radiation.

20. The semiconductor manufacturing tool of claim 17 , wherein the controller is configured to determine a relative position or attitude associated with an overlay of the alignment marks on the substrate and the alignment marks of the virtual mask projected on the substrate based on the image captured by the image capturing device.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Wen-Yun
• Lin Hua-Tai
• Liu Chia-Chu

Classifications

• H10W46/501

  for use before dicing · CPC title

• H10W46/301

  for alignment · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• G03F7/705

  Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions · CPC title