Method for manufacturing semiconductor device and system for performing the same

Patent metadata

Field	Value
Publication number	US-10859924-B2
Application number	US-201815965251-A
Country	US
Kind code	B2
Filing date	Apr 27, 2018
Priority date	Nov 15, 2017
Publication date	Dec 8, 2020
Grant date	Dec 8, 2020

Abstract

A method for manufacturing a structure on a substrate includes projecting an image of a reference pattern onto a substrate having a first patterned layer, the first patterned layer including first alignment marks and first overlay measurement marks, and the reference pattern including second alignment marks and second overlay measurement marks, aligning, based on the first alignment marks and the second alignment marks, the first patterned layer to the image of the reference pattern, obtaining a pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks, and determining compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.

First claim

What is claimed is:

1. A method for manufacturing a structure on a substrate, the method comprising:
projecting an image of a reference pattern onto a substrate having a first patterned layer, the first patterned layer including first alignment marks and first overlay measurement marks, and the reference pattern including second alignment marks and second overlay measurement marks;
aligning, based on the first alignment marks and the second alignment marks, the first patterned layer to the image of the reference pattern;
obtaining a pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks; and
determining compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.

2. The method of claim 1 , further comprising adjusting, based on the compensation data, a parameter in a tool.

3. The method of claim 2 , wherein the tool is an alignment module in a lithography tool.

4. The method of claim 2 , further comprising coating a photoresist layer on the first patterned layer.

5. The method of claim 4 , further comprising:
after coating the photoresist layer, aligning a photomask to the first patterned layer; and
after aligning the photomask to the first patterned layer, patterning the photoresist layer.

6. The method of claim 5 , wherein the parameter is applied in the alignment of the photomask to the first patterned layer.

7. The method of claim 5 , further comprising:
prior to patterning the photoresist layer, forming a second material layer between the first patterned layer and the photoresist layer; and
after patterning the photoresist layer, etching the second material layer with the patterned photoresist layer as an etching mask.

8. The method of claim 7 , further comprising obtaining an overlay mapping of the first overlay measurement marks and third overlay measurement marks in the etched second material layer.

9. The method of claim 8 , further comprising determining another compensation data indicative of information of the overlay mapping of the first overlay measurement marks and the third overlay measurement marks.

10. The method of claim 9 , further comprising adjusting, based on the another compensation data, the parameter in the tool or another parameter in the tool.

11. The method of claim 5 , further comprising:
generating, based on pattern data, a signal indicative of locations of the second alignment marks, and
in response to the generated signal, adjusting an optical system above the substrate to allow the image of the reference pattern projected onto the substrate to be aligned to the first patterned layer.

12. The method of claim 11 , wherein the photomask is manufactured based on the pattern data.

13. The method of claim 4 , wherein the photoresist is coated prior to obtaining the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks, and is exposed after obtaining the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.

14. The method of claim 4 , wherein the photoresist is coated after obtaining the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks, and is exposed after obtaining the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks.

15. The method of claim 2 , wherein the tool is one of an e-beam writer, a nano imprinter, or a self-assembling machine.

16. A method for manufacturing a semiconductor device, comprising:
projecting an image of a reference pattern onto a substrate,
virtually aligning a first patterned layer to the projected image based on first alignment marks in the first patterned layer and second alignment marks provided by the projected image,
obtaining a pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks;
determining compensation data indicative of information of the pre-overlay mapping of the first overlay measurement marks and the second overlay measurement marks;
aligning a virtual photomask to the first patterned layer based on the compensation data;
exposing a photoresist layer coated on the first patterned layer; and
developing the exposed photoresist layer.

17. The method according to claim 16 , wherein two or more coarse alignment marks of the virtual mask are projected onto a surface of the photoresist layer.

18. The method according to claim 17 , further comprising:
capturing an image of coarse alignment marks in the photoresist layer and the two or more coarse alignment marks of the virtual mask projected onto the surface of the photoresist layer; and
determining the relative positions of the coarse alignment marks in the photoresist layer and the coarse alignment marks of the virtual mask projected onto the surface of the photoresist layer to generate the compensation data.

19. A method for manufacturing a semiconductor device, comprising:
forming a photoresist layer over a pattern on a substrate;
virtually aligning a projected image having projected alignment marks with first alignment marks in the pattern on the substrate;
measuring a pre-overlay of projected alignment marks and the first alignment marks;
determining compensation data based on the measuring a pre-overlay;
aligning a mask over the photoresist layer based on the compensation data;
exposing the photoresist layer using the mask, after the aligning the mask;
developing the exposed photoresist layer to form a patterned photoresist layer; and
measuring the overlay of the patterned photoresist layer and the pattern on the substrate.

20. The method according to claim 19 , wherein the mask is a virtual mask.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Wen-Yun
• Lin Hua-Tai
• Liu Chia-Chu

Classifications

• H10W46/501

  for use before dicing · CPC title

• H10W46/301

  for alignment · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• G03F9/7003

  Alignment type or strategy, e.g. leveling, global alignment · CPC title