System and method for lithography patterning

Patent metadata

Field	Value
Publication number	US-9360778-B2
Application number	US-201213411245-A
Country	US
Kind code	B2
Filing date	Mar 2, 2012
Priority date	Mar 2, 2012
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

Disclosed is a lithography system. The lithography system includes a lithography exposure tool designed for performing an exposure process to a radiation-sensitive material layer coated on an integrated circuit substrate; an alignment module coupled with the lithography exposure tool, designed for alignment measurement, and configured for transferring the integrated circuit substrate to the lithography exposure tool; and an alignment calibration module designed to calibrate the alignment module relative to the lithography exposure.

First claim

What is claimed is:

1. A lithography system, comprising:
a lithography exposure tool designed for performing an exposure process to a radiation-sensitive material layer coated on an integrated circuit substrate, wherein the lithography exposure tool includes an exposure substrate stage such that the integrated circuit substrate is disposed on the exposure substrate stage during performing of the exposure process to the radiation-sensitive material layer coated on the integrated circuit substrate, wherein the lithography exposure tool further includes an embedded alignment unit having a first alignment substrate stage and configured for performing a first alignment process on the integrated circuit substrate such that the integrated circuit substrate is disposed on the first alignment substrate stage during performing of the first alignment process on the integrated circuit substrate, wherein the embedded alignment unit is configured to provide the integrated circuit substrate to the exposure substrate stage after performing the first alignment process on the integrated circuit substrate;
an alignment module coupled with the lithography exposure tool, designed for alignment measurement, and configured for transferring the integrated circuit substrate to the lithography exposure tool, wherein the alignment module is separate from and disposed outside of the lithography exposure tool, wherein the alignment module includes a clamping mechanism and a second alignment substrate stage such that the integrated circuit substrate is disposed on the second alignment substrate stage during a second alignment process performed by the alignment module, wherein the alignment module is configured to provide the integrated circuit substrate to the first alignment substrate stage after performing the second alignment process on the integrated circuit substrate; and
an alignment calibration module designed to calibrate the alignment module relative to the lithography exposure tool, wherein calibrating the measured alignment includes performing a tuning process that uses a tuning amount to tune the clamping mechanism to eliminate or reduce a clamping difference induced by the clamping mechanism during the second alignment process.

2. The lithography system of claim 1 , wherein the alignment module includes a number of alignment units, wherein the number is a function of process throughput of the lithography exposure tool.

3. The lithography system of claim 2 , wherein the number of alignment units are configured in parallel for alignment measurement.

4. The lithography system of claim 1 , wherein the lithography exposure tool includes an exposure unit for the exposure process.

5. The lithography system of claim 4 , wherein the alignment calibration module is designed to calibrate difference between the embedded alignment unit and the alignment module.

6. The lithography system of claim 1 , further comprising a track unit designed for coating, baking and developing.

7. The lithography system of claim 6 , wherein the alignment module is distributed in the track unit and is integrated with the track unit.

8. The lithography system of claim 1 , further comprising an overlay measurement tool designed to measure overlay error after developing.

9. The lithography system of claim 8 , wherein the alignment calibration module is distributed in and integrated with the overlay measurement tool.

10. A lithography system for lithography patterning, comprising:
a scanner designed for performing a lithography exposure process to a resist layer coated on a wafer, wherein the scanner includes an exposure wafer stage such that the wafer is disposed on the exposure wafer stage during performing of the lithography exposure process to the resist layer coated on the wafer, wherein the scanner further includes an embedded alignment unit having a first alignment wafer stage and configured for performing a first alignment process on the wafer such that the wafer is disposed on the first alignment wafer stage during performing of the first alignment process on the wafer, wherein the embedded alignment unit is configured to provide the wafer to the exposure wafer stage after performing the first alignment process on the wafer;
an alignment module coupled with the scanner and designed to perform an alignment measurement to the wafer, wherein the alignment module is separate from and disposed outside of the scanner, wherein the alignment module includes a clamping mechanism and a second alignment wafer stage such that the wafer is disposed on the second alignment wafer stage during a second alignment process performed by the alignment module, wherein the alignment module is configured to provide the wafer to the first alignment wafer stage after performing the second alignment process on the wafer;
a track unit designed for processing the resist layer and coupled with the alignment module; and
an alignment calibration module designed to calibrate the alignment measured by the alignment module to alignment experienced by the wafer in the scanner during the lithography exposure process, wherein calibrating the measured alignment includes performing a tuning process that uses a tuning amount to tune the clamping mechanism to eliminate or reduce a clamping difference induced by the clamping mechanism during the second alignment process.

11. The lithography system of claim 10 , wherein the alignment module includes a plurality of alignment units configured in parallel.

12. The lithography system of claim 11 , wherein the number of the alignment units is a function of throughput of the lithography exposure process of the scanner.

13. The lithography system of claim 11 , wherein the scanner includes
an exposure module having a radiation source and an optical assembly configured to perform the lithography exposure process.

14. The lithography system of claim 13 , wherein each of the alignment units includes
a wafer stage to hold the wafer in the respective alignment unit; and
an alignment sensor configured to receive an alignment signal from the wafer.

15. The lithography system of claim 14 , wherein the alignment sensor is designed with a mechanism selected from one of diffraction, imaging and scatterometry.

16. The lithography system of claim 10 , further comprising an overlay measurement tool for overlay measurement after developing of the resist layer.

17. The lithography system of claim 16 , wherein a control module is operable to dynamically tilt a reticle stage during an exposure process.

18. A method for a lithography system, comprising:
coating a wafer with a resist layer;
performing a first alignment measurement in an alignment module, wherein the alignment module is separate from and disposed outside of a lithography exposure tool, wherein the alignment module includes a first alignment wafer stage such that the wafer is disposed on the first alignment wafer stage during performing of the first alignment measurement;
performing a second alignment measurement in an alignment unit embedded in the lithography exposure tool, wherein the alignment unit has a clamping mechanism and a second alignment wafer stage such that the wafer is disposed on the second alignment wafer stage during performing of the second alignment measurement;
performing a tuning process in the embedded alignment unit, wherein the tuning process includes using a tuning amount to tune the clamping mechanism to eliminate or reduce a clamping difference induced by the clamping mechanism during the second alignment measurement;
performin

Assignees

• Chen Li-Jui
• Liang Fu-Jye
• Wu Hsueh-Hung
• Taiwan Semiconductor Mfg

Inventors

• Chen Li-Jui
• Liang Fu-Jye
• Wu Hsueh-Hung

Classifications

• G03F9/7096 Primary

  Arrangement, mounting, housing, environment, cleaning or maintenance of apparatus · CPC title

• G03F9/7019

  Calibration · CPC title