Scanner overlay correction system and method

Patent metadata

Field	Value
Publication number	US-9442392-B2
Application number	US-201414585457-A
Country	US
Kind code	B2
Filing date	Dec 30, 2014
Priority date	Dec 17, 2012
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

A method of processing first and second semiconductor wafers is provided. Each of the first and second semiconductor wafers has a first layer and a second layer over the first layer. A first lithographic process is performed on the first layer over the first semiconductor wafer using a first inter-field correction and a first intra-field correction. An overlay error of the first lithographic process is determined. A second inter-field correction and a second intra-field correction are computed based on the first inter-field correction, the first intra-field correction, and the measured overlay error. A second lithographic process is performed on the second layer over the second semiconductor wafer, based on the second inter-field correction and the second intra-field correction.

First claim

What is claimed is:

1. A method of processing first and second semiconductor wafers, each having a first layer thereon and a second layer over the first layer, the method comprising:
performing a first lithographic process on the first layer over the first semiconductor wafer using a first inter-field correction and a first intra-field correction;
determining an overlay error of the first lithographic process;
computing a second inter-field correction and a second intra-field correction based on the first inter-field correction, the first intra-field correction, and the measured overlay error;
performing a second lithographic process on the second layer over the second semiconductor wafer, based on the second inter-field correction and the second intra-field correction.

2. The method of claim 1 , further comprising
computing a third inter-field correction and a third intra-field correction based on the first and second inter-field corrections and the first and second intra-field corrections; and
performing a third lithographic process on a second layer over a first layer over a third semiconductor wafer.

3. The method of claim 2 , wherein the third intra-field correction is computed using exponential weighted moving average of the first and second intra-field corrections.

4. The method of claim 1 , wherein the computing step includes:
subtracting measured data of the first semiconductor wafer from corresponding target data to provide a residue; and
subtracting the first intra-field correction from the residue to provide an intra-field offset of the second layer of the second wafer.

5. The method of claim 4 , wherein the computing step further includes:
computing an inverse of the intra-field offset of the second layer of the second wafer to provide the second intra-field correction.

6. The method of claim 5 , further comprising combining the second intra-field correction with the first intra-field correction to determine a control action used to process the second wafer.

7. The method of claim 1 , further comprising
computing an Nth intra-field correction, where N is an integer greater than 2, based on intra-field corrections corresponding to respective second layers of a plurality of semiconductor wafers including the first semiconductor wafer, and an N−1th semiconductor wafer; and
performing a lithographic process on a second layer over a first layer over the Nth semiconductor wafer using the Nth intra-field correction.

8. The method of claim 7 , wherein each of the plurality of semiconductor wafers is included in a respectively different lot of semiconductor wafers.

9. A method for processing a plurality of lots of semiconductor wafers, each lot having a plurality of semiconductor wafers, each semiconductor wafer having a first layer thereon and a second layer over the first layer, the method comprising:
performing a lithographic process on the semiconductor wafers using at least one semiconductor fabrication tool;
adjusting one or more parameters of the semiconductor fabrication tool, the controller configured for:
performing the lithographic process on the second layer of each semiconductor wafer in the first lot using a first intra-field correction;
determining an overlay error of the lithographic process based on data sampled from the first lot; and
computing at least two different intra-field corrections corresponding to at least two other respective lots within the plurality of lots based in part on the first intra-field correction.

10. The method of claim 9 , wherein the computing step uses an exponential weighted moving average of intra-field corrections for each completed one of the plurality of lots to compute an intra-field correction to be used for performing the lithographic process on a next one of the plurality of lots.

11. The method of claim 9 , wherein the semiconductor fabrication tool is a scanner.

12. The method of claim 9 , wherein determining the overlay error includes:
receiving measurements of a plurality of values in each of a plurality of fields within at least one wafer within the first one of the plurality of lots;
comparing the measurements to respective target values;
computing a standard deviation of each of the plurality of values across the plurality of fields.

13. The method of claim 12 , wherein determining the overlay error further includes computing a residue array, such that each value in the residue array is three times the standard deviation of a respective one of the plurality of values.

14. The method of claim 9 , wherein:
the method further comprises separating the overlay error into an inter-field error and an intra-field error,
the step of causing the tool to perform the lithographic process on the second layer includes applying an inter-field correction, and
the at least two different intra-field corrections are based in part on the intra-field error.

15. A method comprising:
performing a lithographic process on a pre-determined layer over each wafer in at least first, second and third lots of semiconductor wafers;
computing an intra-field correction of semiconductor wafers in the first lot based on measurement data from the first lot; and
computing respectively different intra-field corrections for each respective one of the second and third lots of wafers, the intra-field correction of the second lot based in part on the intra-field correction of the first lot, the intra-field correction of the third lot based in part on the intra-field correction of the first lot and the intra-field correction of the second lot, the second and third intra-field corrections being applied to perform the lithographic process on the second and third lots, respectively.

16. The method of claim 15 , wherein the third intra-field correction is computed using an exponential weighted moving average of the first and second intra-field corrections.

17. The method of claim 15 , wherein the lithographic tool processes one or more additional lots of semiconductor wafers using a respectively different additional intra-field correction for each additional lot, and each of the additional intra-field corrections is based in part on each respective one of the intra-field corrections applied in processing each previously processed lot of semiconductor wafers among the first, second, third and additional lots.

18. The method of claim 15 , wherein the method includes:
subtracting the measurement data of the first lot from corresponding target intra-field data to provide a residue;
subtracting the intra-field correction of the first lot from the residue to provide an intra-field offset of the pre-determined layer of the second lot;
computing an inverse of the intra-field offset of the pre-determined layer of the second lot to provide the second intra-field correction; and
combining the second intra-field correction to the first intra-field correction to determine a control action used to process the second lot.

19. The method of claim 15 , the method comprises computing an overlay error based on the measurement data, and dividing the overlay error into the intra-field error and an inter-field error.

20. The method of claim 19 , wherein:
the method comprises computing an inter-field correction for each of the lots; and
the intra-field correction for each lot is in part based on the inter-field correction and intra-field correction corresponding to a layer adjacent to the pre-determined layer in each one of the lots that has already been processed by the semiconduc

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsen Yen-Di
• Hsieh Yi-Ping
• Huang Chen-Yen
• Lu Shin-Rung
• Mou Jong-I

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P76/2041

  Photolithographic processes · CPC title

• G03F9/7019

  Calibration · CPC title

• G03F9/7003

  Alignment type or strategy, e.g. leveling, global alignment · CPC title