Crack detection integrity check

Patent metadata

Field	Value
Publication number	US-11366156-B2
Application number	US-202016746201-A
Country	US
Kind code	B2
Filing date	Jan 17, 2020
Priority date	Jan 24, 2019
Publication date	Jun 21, 2022
Grant date	Jun 21, 2022

Abstract

A method of testing integrated circuit die for presence of a crack includes performing back end integrated circuit fabrication processes on a wafer having a plurality of integrated circuit die, the back end fabrication including an assembly process. The assembly process includes a) lowering a tip of a first manipulator arm to contact a given die such that pogo pins extending from the tip make electrical contact with conductive areas on the given die so that the pogo pins are electrically connected to a crack detector on the given die, b) picking up the given die using the first manipulator arm, and c) performing a conductivity test on the crack detector using the pogo pins to determine presence of a crack in the given die that extends from a periphery of the die, through a die seal ring of the die, and into an integrated circuit region of the die.

First claim

The invention claimed is:

1. A method of testing an integrated circuit die for presence of a crack, the method comprising:
performing back end integrated circuit fabrication processes on a wafer having a plurality of integrated circuit die, the back end integrated circuit fabrication processes including an assembly process, the assembly process comprising steps of:
a) lowering a tip of a first manipulator arm to contact a given integrated circuit die of the plurality of integrated circuit die of the wafer such that pogo pins extending from the tip make electrical contact with conductive areas on the given integrated circuit die so that the pogo pins are electrically connected to a crack detector on the given integrated circuit die;
b) performing a conductivity test on the crack detector using the pogo pins;
c) if the conductivity test indicates a lack of presence of a crack in the given integrated circuit die, picking up the given integrated circuit die using the first manipulator arm; and
d) if the conductivity test indicates presence of a crack in the given integrated circuit die, raising the tip of the first manipulator arm without picking up the given integrated circuit die, moving the first manipulator arm to a next given integrated circuit die, and repeating steps a), b), c) and d) on the next given integrated circuit die.

2. The method of claim 1 , further comprising, at step c), flipping the given integrated circuit die using the first manipulator arm such that a surface of the given integrated circuit die facing the wafer now faces a different direction, and transferring the given integrated circuit die to a tip of a second manipulator arm, after picking up the given integrated circuit die.

3. The method of claim 1 , wherein the presence of the crack in the given integrated circuit die indicates that the crack extends from a periphery of the given integrated circuit die, through a die seal ring of the given integrated circuit die, and into an integrated circuit region of the given integrated circuit die.

4. The method of claim 1 , wherein the assembly process further comprises steps of:
e) placing the given integrated circuit die into a package;
f) sealing the package; and
g) storing the package.

5. The method of claim 1 , further comprising performing front end integrated circuit fabrication processes to produce the wafer having the plurality of integrated circuit die, prior to performing the back end integrated circuit fabrication processes; and wherein performing the front end integrated circuit fabrication processes includes:
fabricating the wafer to include the plurality of integrated circuit die;
performing a wafer sort operation including testing of the plurality of integrated circuit die, the testing of the plurality of integrated circuit die including, for each of the plurality of integrated circuit die, performing a conductivity test of a crack detector of that integrated circuit chain using test apparatus to determine presence of a crack in that integrated circuit die extending from a periphery of that integrated circuit die, through a die seal ring of that integrated circuit die, and into an integrated circuit region of that integrated circuit die; and
marking any of the plurality of integrated circuit die for which the conductivity test of the crack detector determines presence of a crack.

6. A method of testing an integrated circuit die for presence of a crack, the method comprising:
performing back end integrated circuit fabrication processes on a wafer having a plurality of integrated circuit die, the back end integrated circuit fabrication processes including an assembly process, the assembly process comprising steps of:
a) lowering a tip of a first manipulator arm to contact a given integrated circuit die of the plurality of integrated circuit die of the wafer such that pogo pins extending from the tip make electrical contact with conductive areas on the given integrated circuit die so that the pogo pins are electrically connected to a crack detector on the given integrated circuit die;
b) performing a conductivity test on the crack detector using the pogo pins;
c) if the conductivity test indicates a lack of presence of a crack in the given integrated circuit die, picking up the given integrated circuit die using the first manipulator arm; and
d) flipping the given integrated circuit die using the first manipulator arm such that a surface of the given integrated circuit die facing the wafer now faces a different direction, and transferring the given integrated circuit die to a tip of a second manipulator arm, after picking up the given integrated circuit die.

7. The method of claim 6 , wherein the assembly process further comprises steps of:
e) placing the given integrated circuit die into a package;
f) sealing the package; and
g) storing the package.

8. The method of claim 6 , further comprising performing front end integrated circuit fabrication processes to produce the wafer having the plurality of integrated circuit die; and wherein performing the front end integrated circuit fabrication processes includes:
fabricating the wafer to include the plurality of integrated circuit die;
performing a wafer sort operation including testing of the plurality of integrated circuit die, the testing of the plurality of integrated circuit die including, for each of the plurality of integrated circuit die, performing a conductivity test of a crack detector of that integrated circuit chain using test apparatus to determine presence of a crack in that integrated circuit die; and
marking any of the plurality of integrated circuit die for which the conductivity test of the crack detector determines presence of a crack.

9. A method of testing an integrated circuit die for presence of a crack, the method comprising:
performing back end integrated circuit fabrication processes on a wafer having a plurality of integrated circuit die, the back end integrated circuit fabrication processes including an assembly process, the assembly process comprising steps of:
a) lowering a tip of a first manipulator arm to contact a given integrated circuit die of the plurality of integrated circuit die of the wafer such that pogo pins extending from the tip make electrical contact with conductive areas on the given integrated circuit die so that the pogo pins are electrically connected to a crack detector on the given integrated circuit die;
b) performing a conductivity test on the crack detector using the pogo pins; and
c) if the conductivity test indicates presence of a crack in the given integrated circuit die, raising the tip of the first manipulator arm without picking up the given integrated circuit die, moving the first manipulator arm to a next given integrated circuit die, and repeating steps a), b), and c) on the next given integrated circuit die.

10. The method of claim 9 , wherein the presence of the crack in the given integrated circuit die indicates that the crack extends from a periphery of the given integrated circuit die, through a die seal ring of the given integrated circuit die, and into an integrated circuit region of the given integrated circuit die.

Assignees

• St Microelectronics Pte Ltd

Inventors

• Peralta Pedro Jr Santos
• Gani David

Classifications

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• G01R31/318511

  Wafer Test · CPC title

• G01R31/2831 Primary

  Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates (G01R31/318511 takes precedence; testing during manufacture H10P74/00) · CPC title

• G01R31/2601

  Apparatus or methods therefor (G01R31/2607, G01R31/2642 take precedence) · CPC title