Capacitive test device and method for capacitive testing a component

Patent metadata

Field	Value
Publication number	US-9250293-B2
Application number	US-201213544852-A
Country	US
Kind code	B2
Filing date	Jul 9, 2012
Priority date	Jul 9, 2012
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

A system and a method for capacitive testing a component (including a packaged component) are disclosed. An embodiment of a test head comprises a holding unit configured to pick-up, hold and release the component, an electrode configured to receive a capacitive signal from the component and a preamplifier configured to amplify the capacitive signal.

First claim

What is claimed is:

1. A test system for testing a component comprising:
a test tray configured to be loaded with a plurality of components;
a loading board configured to load the components into the test tray from underneath the test tray;
a plurality of pin fixtures configured to move towards the test tray and to provide signals to the components;
a plurality of test heads configured to move towards the test tray and to receive capacitive signals of the components, wherein the pin fixtures and the test heads move from opposite sides to the test tray; and
a controller configured to process the received capacitive signals.

2. The test system according to claim 1 , wherein the test heads comprise a plurality of ring probe electrodes and a plurality of preamplifiers.

3. The test system according to claim 2 , wherein the test heads further comprise a plurality of x-y pushers and a plurality of x-y guides.

4. The test system according to claim 2 , wherein the test heads further comprise a plurality of DUT body guides.

5. The test system according to claim 1 , wherein the pin fixtures comprise a plurality of pogo pins.

6. The test system according to claim 5 , wherein the pogo pins are electrically connected to a power source, and wherein the power source is configured to provide an AC current that generates the capacitive signals.

7. The test system according to claim 1 , wherein the test heads comprise a plurality of guide pins, the guide pins being configured to align the test heads and the test tray.

8. The test system according to claim 1 , wherein each component comprises a semiconductor device disposed on and bonded to a leadframe, the semiconductor device being encapsulated.

9. A test system for testing a component comprising:
a test tray;
a loading board configured to load a component into the test tray from underneath the test tray;
a pin fixture configured to be connected to a bottom side of the component and to provide signals to the component;
a test head configured to be connected to a top side of the component and to receive capacitive signals from the component; and
a controller configured to process the received capacitive signals.

10. The test system according to claim 9 , wherein the test head comprises a plurality of ring probe electrodes and a plurality of preamplifiers.

11. The test system according to claim 10 , wherein the test head further comprises a plurality of x-y pushers and a plurality of x-y guides.

12. The test system according to claim 10 , wherein the test head further comprises a DUT body guide.

13. The test system according to claim 9 , wherein the pin fixture comprises a plurality of pogo pins.

14. The test system according to claim 13 , wherein the pogo pins are electrically connected to a power source, and wherein the power source is configured to provide an AC current that generates the capacitive signals.

15. The test system according to claim 9 , wherein the system further comprises guide pins configured to guide the test head, the test tray and the loading board.

16. The test system according to claim 9 , wherein each component comprises a semiconductor device disposed on and bonded to a leadframe, the semiconductor device being encapsulated.

17. A test system for testing a packaged chip comprising:
a test tray configured to provide a plurality of packaged chips;
a loading board configured to load the plurality of packaged chips into the test tray from underneath the test tray;
a pin fixture configured to provide signals to the plurality of packaged chips;
a test head configured to receive capacitive signals from the plurality of packaged chips; and
a controller configured to process the received capacitive signals,
wherein the test head comprises a plurality of guide pins configured to guide the test head into the test tray.

18. The test system according to claim 17 , wherein the test head further comprises a plurality of x-y pushers and a plurality of x-y guides.

19. The test system according to claim 18 , wherein the test head further comprises a DUT body guide.

20. The test system according to claim 17 , wherein the pin fixture comprises a plurality of pogo pins.

21. The test system according to claim 20 , wherein the pogo pins are electrically connected to a power source, and wherein the power source is configured to provide an AC current that generates the capacitive signals.

Assignees

• Xue Ming
• Kok Weng Yew
• Infineon Technologies Ag

Inventors

• Xue Ming
• Kok Weng Yew

Classifications

• G01R1/07

  Non contact-making probes · CPC title

• G01R31/2893

  Handling, conveying or loading, e.g. belts, boats, vacuum fingers (G01R31/2867 takes precedence; handling semiconductor devices or wafers during manufacture or treatment H10P72/00) · CPC title

• G01R31/312 Primary

  by capacitive methods · CPC title